From ea1eb12a38f09e494d5ef072e55653a6463d57eb Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong <juzhe.zhong@rivai.ai> Date: Wed, 23 Aug 2023 10:11:06 +0800 Subject: [PATCH] RISC-V: Add attribute to vtype change only vsetvl This patch is prepare patch for VSETVL PASS. Commited. gcc/ChangeLog: * config/riscv/vector.md: Add attribute. --- gcc/config/riscv/vector.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e772e79057d1..6ceae25dbedb 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1363,7 +1363,11 @@ "TARGET_VECTOR" "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3" [(set_attr "type" "vsetvl") - (set_attr "mode" "SI")]) + (set_attr "mode" "SI") + (set (attr "sew") (symbol_ref "INTVAL (operands[0])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[2])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))]) ;; vsetvl zero,rs1,vtype instruction. ;; The reason we need this pattern since we should avoid setting X0 register -- GitLab