ChangeLog

2024-12-01  Slava Barinov  <v.barinov@samsung.com>

	* configure.ac: Only remove -O[0-9] if not preceded with comma
	* configure: Regenerated

2024-12-01  Jovan Vukic  <Jovan.Vukic@rt-rk.com>

	* tree-ssa-phiopt.cc (rhs_is_fed_for_value_replacement): Add a new
	optimization opportunity for BIT_IOR_EXPR and a != b.
	(operand_equal_for_value_replacement): Ditto.

2024-12-01  Mariam Arutunian  <mariamarutunian@gmail.com>

	* gimple-crc-optimization.cc (optimize_crc_loop): New function.
	(execute): Add optimize_crc_loop function call.

2024-12-01  Mariam Arutunian  <mariamarutunian@gmail.com>

	* Makefile.in (OBJS): Add crc-verification.o.
	* crc-verification.cc: New file.
	* crc-verification.h: New file.
	* gimple-crc-optimization.cc (loop_calculates_crc): New function.
	(is_output_crc): Likewise.
	(swap_crc_and_data_if_needed): Likewise.
	(validate_crc_and_data): Likewise.
	(optimize_crc_loop): Likewise.
	(get_output_phi): Likewise.
	(execute): Add check whether potential CRC loop calculates CRC.
	* sym-exec/sym-exec-state.cc (create_reversed_lfsr): New function.
	(create_forward_lfsr): Likewise.
	(last_set_bit): Likewise.
	(create_lfsr): Likewise.
	* sym-exec/sym-exec-state.h (is_bit_vector): Reorder, make the function public and static.
	(create_reversed_lfsr) New static function declaration.
	(create_forward_lfsr) New static function declaration.

2024-12-01  Matevos Mehrabyan  <matevosmehrabyan@gmail.com>

	* Makefile.in (OBJS): Add sym-exec/sym-exec-expression.o,
	sym-exec/sym-exec-state.o, sym-exec/sym-exec-condition.o.
	* configure (sym-exec): New subdir.
	* sym-exec/sym-exec-condition.cc: New file.
	* sym-exec/sym-exec-condition.h: New file.
	* sym-exec/sym-exec-expr-is-a-helper.h: New file.
	* sym-exec/sym-exec-expression.cc: New file.
	* sym-exec/sym-exec-expression.h: New file.
	* sym-exec/sym-exec-state.cc: New file.
	* sym-exec/sym-exec-state.h: New file.
	Co-authored-by: Mariam Arutunian <mariamarutunian@gmail.com>

2024-12-01  Mariam Arutunian  <mariamarutunian@gmail.com>

	* Makefile.in (OBJS): Add gimple-crc-optimization.o.
	* common.opt (foptimize-crc): New option.
	* common.opt.urls: Regenerate to add foptimize-crc.
	* doc/invoke.texi (-foptimize-crc): Add documentation.
	* gimple-crc-optimization.cc: New file.
	* opts.cc (default_options_table): Add OPT_foptimize_crc.
	(enable_fdo_optimizations): Enable optimize_crc.
	* passes.def (pass_crc_optimization): Add new pass.
	* timevar.def (TV_GIMPLE_CRC_OPTIMIZATION): New timevar.
	* tree-pass.h (make_pass_crc_optimization): New extern function
	declaration.

2024-12-01  Mark Harmstone  <mark@harmstone.com>

	* configure.ac (HAVE_GAS_CV_UCOMP): New check.
	* configure: Regenerate.
	* config.in: Regenerate.
	* dwarf2codeview.cc (enum binary_annotation_opcode): Define.
	(struct codeview_function): Add htab_next and inline_loc;
	(struct cv_func_hasher): Define.
	(cv_func_htab): New global variable.
	(new_codeview_function): Add new codeview_function to hash table.
	(codeview_begin_block): Record location of inline block.
	(codeview_end_block): Add dummy source line at end of inline block.
	(find_line_function): New function.
	(write_binary_annotations): New function.
	(write_s_inlinesite): Call write_binary_annotations.
	(codeview_debug_finish): Delete cv_func_htab.

2024-12-01  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/117859
	* tree-ssa-sccvn.cc (insert_predicates_for_cond): If the
	valueization for the new lhs for `lhs != 0`
	is the same as the old ones, don't recurse.

2024-12-01  Andrew Pinski  <quic_apinski@quicinc.com>

	* tree-ssa-loop-im.cc (move_computations_worker): While moving
	phi, reuse the lhs of the conditional if it is a boolean type.

2024-12-01  Alexey Merzlyakov  <alexey.merzlyakov@samsung.com>

	PR rtl-optimization/112398
	PR rtl-optimization/117476
	* simplify-rtx.cc (simplify_context::simplify_unary_operation_1):
	Simplify ZERO_EXTEND (SUBREG (NOT X)) to XOR (X, GET_MODE_MASK(SUBREG))
	when X doesn't have any non-zero bits outside of SUBREG mode.

2024-11-30  Lewis Hyatt  <lhyatt@gmail.com>

	* diagnostic-show-locus.cc
	(test_one_liner_fixit_validation_adhoc_locations): Adapt so it can
	effectively test 7-bit ranges instead of 5-bit ranges.
	(test_one_liner_fixit_validation_adhoc_locations_utf8): Likewise.
	* input.cc (get_end_location): Adjust types to support 64-bit
	location_t.
	(write_digit_row): Likewise.
	(dump_location_range): Likewise.
	(dump_location_info): Likewise.
	(class line_table_case): Likewise.
	(test_accessing_ordinary_linemaps): Replace some hard-coded
	constants with the values defined in line-map.h.
	(for_each_line_table_case): Likewise.

2024-11-30  Lewis Hyatt  <lhyatt@gmail.com>

	* toplev.cc (general_init): Replace hard-coded constant with
	line_map_suggested_range_bits.

2024-11-30  Lewis Hyatt  <lhyatt@gmail.com>

	* config/aarch64/aarch64-c.cc (aarch64_resolve_overloaded_builtin):
	Change "unsigned int" argument to "location_t".
	* config/avr/avr-c.cc (avr_resolve_overloaded_builtin): Likewise.
	* config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Likewise.
	* target.def: Likewise.
	* doc/tm.texi: Regenerate.

2024-11-30  Joseph Myers  <josmyers@redhat.com>
	    Richard Biener  <rguenther@suse.de>

	PR c/100501
	PR c/100792
	* gimplify.cc (gimplify_asm_expr): Handle void expressions for
	memory inputs like other non-lvalues.

2024-11-30  Mark Harmstone  <mark@harmstone.com>

	* dwarf2codeview.cc (enum cv_sym_type): Add S_INLINESITE and
	S_INLINESITE_END.
	(get_func_id): Add declaration.
	(write_s_inlinesite): New function.
	(write_inlinesite_records): New function.
	(write_function): Call write_inlinesite_records.

2024-11-30  Mark Harmstone  <mark@harmstone.com>

	* dwarf2codeview.cc (DEBUG_S_INLINEELINES): Define.
	(CV_INLINEE_SOURCE_LINE_SIGNATURE): Define.
	(struct codeview_inlinee_lines): Define.
	(struct inlinee_lines_hasher): Define.
	(func_htab, inlinee_lines_htab): New global variables.
	(get_file_id): New function.
	(codeview_source_line): Move file_id logic to get_file_id.
	(write_inlinee_lines_entry): New function.
	(write_inlinee_lines): New function.
	(codeview_debug_finish): Call write_inlinee_lines, and free func_htab
	and inlinee_lines_htab.
	(get_func_id): New function.
	(add_function): Move func_id logic to get_func_id.
	(codeview_abstract_function): New function.
	* dwarf2codeview.h (codeview_abstract_function): Add declaration.
	* dwarf2out.cc (dwarf2out_abstract_function): Call
	codeview_abstract_function if outputting CodeView debug info.

2024-11-30  Mark Harmstone  <mark@harmstone.com>

	* dwarf2codeview.cc (struct codeview_function): Add parent and
	inline_block fields.
	(cur_func): New global variable.
	(new_codeview_function): New function.
	(codeview_source_line): Call new_codeview_function, and use cur_func
	instead of last_func.
	(codeview_begin_block): New function.
	(codeview_end_block): New function.
	(write_line_numbers): No longer free data as we go along.
	(codeview_switch_text_section): Call new_codeview_function, and use
	cur_func instead of last_func.
	(codeview_end_epilogue): Use cur_func instead of last_func.
	(codeview_debug_finish): Free funcs list and its contents.
	* dwarf2codeview.h (codeview_begin_block): Add declaration.
	(codeview_end_block): Add declaration.
	* dwarf2out.cc (dwarf2out_begin_block): Call codeview_begin_block if
	outputting CodeView debug info.
	(dwarf2out_end_block): Call codeview_end_block if outputting CodeView
	debug info.

2024-11-30  Mark Harmstone  <mark@harmstone.com>

	* debug.cc (do_nothing_debug_hooks): Change begin_block
	function pointer.
	(debug_nothing_int_int_tree): New function.
	* debug.h (struct gcc_debug_hooks): Add tree parameter to begin_block.
	(debug_nothing_int_int_tree): Add declaration.
	* dwarf2out.cc (dwarf2out_begin_block): Add tree parameter.
	(dwarf2_lineno_debug_hooks): Use new dummy function for begin_block.
	* final.cc (final_scan_insn_1): Pass insn block through to
	debug_hooks->begin_block.
	* vmsdbgout.cc (vmsdbgout_begin_block): Add tree parameter.

2024-11-30  Georg-Johann Lay  <avr@gjlay.de>

	PR target/84211
	* config/avr/avr-passes.cc (try_split_any) [SET, MOVW]: Prefer
	reg=reg move over reg=const when splitting a reg=reg insn.

2024-11-30  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/117057
	* tree-ssa-strlen.cc (strlen_pass::count_nonzero_bytes): Punt also
	when byte_size is equal to offset or nchars.  Punt if offset is bigger
	than INT_MAX.  Handle vector CONSTRUCTOR with some elements constant,
	possibly followed by non-constant.

2024-11-30  Jakub Jelinek  <jakub@redhat.com>

	PR libgomp/117851
	* lto-wrapper.cc (find_crtoffloadtable): Add PIE_OR_SHARED argument,
	search for crtoffloadtableS.o rather than crtoffloadtable.o if
	true.
	(run_gcc): Add pie_or_shared variable.  If OPT_pie or OPT_shared or
	OPT_static_pie is seen, set pie_or_shared to true, if OPT_no_pie is
	seen, set pie_or_shared to false.  Pass it to find_crtoffloadtable.

2024-11-30  Jinyang He  <hejinyang@loongson.cn>

	* config/loongarch/constraints.md (Uuv6, Uuvx): Remove Uuv6,
	add Uuvx as replicated vector const with unsigned range [0,umax].
	* config/loongarch/lasx.md (xvsrl, xvsra, xvsll): Mask shift
	offset by its unit bits.
	* config/loongarch/lsx.md (vsrl, vsra, vsll): Likewise.
	* config/loongarch/loongarch-protos.h
	(loongarch_const_vector_same_int_p): Set default for low and high.
	* config/loongarch/predicates.md: Replace reg_or_vector_same_uimm6
	_operand to reg_or_vector_same_uimm_operand.

2024-11-30  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/117360
	* ext-dce.cc (ext_dce_process_sets): Use HOST_WIDE_INT_UC
	macro instead of ULL suffixed constants.
	(carry_backpropagate): Likewise.  Use HOST_WIDE_INT_1U instead of
	1ULL.  Use GET_MODE_BITSIZE (smode) instead of
	GET_MODE_BITSIZE (mode) and with that avoid having to use
	known_lt instead of < or use .to_constant ().  Formatting fixes.
	(case SIGN_EXTEND): Set mode to GET_MODE_INNER (GET_MODE (XEXP (x, 0)))
	rather than GET_MODE (XEXP (x, 0)) and don't use GET_MODE_INNER (mode).
	(ext_dce_process_uses): Use HOST_WIDE_INT_UC macro instead of ULL
	suffixed constants.

2024-11-30  Jakub Jelinek  <jakub@redhat.com>

	* doc/invoke.texi (-Wdeprecated-variadic-comma-omission): Document.

2024-11-29  David Malcolm  <dmalcolm@redhat.com>

	* Makefile.in: Rename "libdiagnostics" to "libgdiagnostics".
	* configure.ac: Likewise.
	* configure: Regenerate.
	* doc/install.texi: Rename "libdiagnostics" to
	"libgdiagnostics".
	* doc/libdiagnostics/*: Rename to doc/libgdiagnostics, renaming
	"libdiagnostics" to "libgdiagnostics" throughout.
	* libdiagnostics++.h: Rename to...
	* libgdiagnostics++.h: ...this, renaming "libdiagnostics" to
	"libgdiagnostics" throughout.
	* libdiagnostics.cc: Rename to...
	* libgdiagnostics.cc: ...this, renaming "libdiagnostics" to
	"libgdiagnostics" throughout.
	* libdiagnostics.h: Rename to...
	* libgdiagnostics.h: ...this, renaming "libdiagnostics" to
	"libgdiagnostics" throughout.
	* libdiagnostics.map: Rename to...
	* libgdiagnostics.map: ...this, renaming "libdiagnostics" to
	"libgdiagnostics" throughout.
	* libsarifreplay.cc: Update for renaming of "libdiagnostics"
	to "libgdiagnostics".
	* libsarifreplay.h: Likewise.
	* sarif-replay.cc: Likewise.
	* doc/libgdiagnostics/Makefile: New file.
	* doc/libgdiagnostics/conf.py: New file.
	* doc/libgdiagnostics/index.rst: New file.
	* doc/libgdiagnostics/make.bat: New file.
	* doc/libgdiagnostics/topics/diagnostic-manager.rst: New file.
	* doc/libgdiagnostics/topics/diagnostics.rst: New file.
	* doc/libgdiagnostics/topics/execution-paths.rst: New file.
	* doc/libgdiagnostics/topics/fix-it-hints.rst: New file.
	* doc/libgdiagnostics/topics/index.rst: New file.
	* doc/libgdiagnostics/topics/logical-locations.rst: New file.
	* doc/libgdiagnostics/topics/message-formatting.rst: New file.
	* doc/libgdiagnostics/topics/metadata.rst: New file.
	* doc/libgdiagnostics/topics/physical-locations.rst: New file.
	* doc/libgdiagnostics/topics/retrofitting.rst: New file.
	* doc/libgdiagnostics/topics/sarif.rst: New file.
	* doc/libgdiagnostics/topics/text-output.rst: New file.
	* doc/libgdiagnostics/topics/ux.rst: New file.
	* doc/libgdiagnostics/tutorial/01-hello-world.rst: New file.
	* doc/libgdiagnostics/tutorial/02-physical-locations.rst: New file.
	* doc/libgdiagnostics/tutorial/03-logical-locations.rst: New file.
	* doc/libgdiagnostics/tutorial/04-notes.rst: New file.
	* doc/libgdiagnostics/tutorial/05-warnings.rst: New file.
	* doc/libgdiagnostics/tutorial/06-fix-it-hints.rst: New file.
	* doc/libgdiagnostics/tutorial/07-execution-paths.rst: New file.
	* doc/libgdiagnostics/tutorial/example-1.png: New file.
	* doc/libgdiagnostics/tutorial/index.rst: New file.

2024-11-29  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-c.cc: Fix some coding rule nits and typos.
	* config/avr/avr-passes.cc: Same
	* config/avr/avr.h: Same.
	* config/avr/avr.cc: Same.
	(avr_function_arg_regno_p, avr_hard_regno_rename_ok)
	(avr_epilogue_uses, extra_constraint_Q): Return bool instead of int.
	* config/avr/avr-protos.h (avr_function_arg_regno_p)
	(avr_hard_regno_rename_ok, avr_epilogue_uses)
	(extra_constraint_Q): Return bool instead of int.

2024-11-29  Andrew Pinski  <quic_apinski@quicinc.com>

	* config/aarch64/aarch64-builtins.cc (aarch64_init_data_intrinsics): Call
	aarch64_get_attributes and update calls to aarch64_general_add_builtin.

2024-11-29  Andrew Pinski  <quic_apinski@quicinc.com>

	* config/aarch64/aarch64-builtins.cc (aarch64_init_prefetch_builtin):
	Updete call to aarch64_general_add_builtin in AARCH64_INIT_PREFETCH_BUILTIN.
	Add new variable prefetch_attrs.

2024-11-29  Andrew Pinski  <quic_apinski@quicinc.com>

	* config/aarch64/aarch64-builtins.cc (VREINTERPRET_BUILTIN): Use
	FLAG_NONE instead of FLAG_AUTO_FP.
	(VGET_LOW_BUILTIN): Likewise.
	(VGET_HIGH_BUILTIN): Likewise.

2024-11-29  Andrew Pinski  <quic_apinski@quicinc.com>

	PR target/117665
	* config/aarch64/aarch64-builtins.cc (aarch64_init_simd_builtin_functions):
	Pass nothrow and leaf as attributes to aarch64_general_add_builtin for
	__builtin_aarch64_im_lane_boundsi.

2024-11-29  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/117770
	* lra-lives.cc: Include ira-int.h.
	(process_bb_lives): Check hard regs corresponding insn operands
	for dying hard wired reg clobbers.

2024-11-29  Georg-Johann Lay  <avr@gjlay.de>

	PR target/117681
	* config/avr/avr.cc (TARGET_UNWIND_WORD_MODE): Define to...
	(avr_unwind_word_mode): ...this new static function.

2024-11-29  Georg-Johann Lay  <avr@gjlay.de>

	PR target/117726
	* config/avr/avr-passes.cc (avr_shift_is_3op, avr_emit_shift):
	Also handle 2-byte and 3-byte shifts.
	(avr_split_shift4, avr_split_shift3, avr_split_shift2): New
	local helper functions.
	(avr_split_shift): Use them.
	* config/avr/avr-passes.def (avr_pass_split_after_peephole2):
	Adjust comments.
	* config/avr/avr.cc (avr_out_ashlpsi3, avr_out_ashrpsi3)
	(avr_out_lshrpsi3): Support offset 15.
	(ashrhi3_out): Support offset 7 as 3-op.
	(ashrsi3_out): Support offset 15.
	(avr_rtx_costs_1): Adjust shift costs.
	* config/avr/avr.md (2op): Remove attribute value and all such insn
	alternatives.
	(ashlhi3, *ashlhi3, *ashlhi3_const): Add 3-op alternatives like C2l.
	(ashrhi3, *ashrhi3, *ashrhi3_const): Add 3-op alternatives like C2a.
	(lshrhi3, *lshrhi3, *lshrhi3_const): Add 3-op alternatives like C2r.
	(*ashlpsi3_split, *ashlpsi3): Add 3-op alternatives C15 and C3l.
	(*ashrpsi3_split, *ashrpsi3): Add 3-op alternatives C15 and C3r.
	(*lshrpsi3_split, *lshrpsi3): Add 3-op alternatives C15 and C3r.
	(ashlsi3, *ashlsi3, *ashlsi3_const): Remove "2op" alternative.
	(ashrsi3, *ashrsi3, *ashrsi3_const): Same.
	(lshrsi3, *lshrsi3, *lshrsi3_const): Same.
	(constr_split_suffix): Code attr morphed from constr_split_shift4.
	* config/avr/constraints.md (C2a, C2r, C2l)
	(C3a, C3r, C3l): New constraints.
	* doc/invoke.texi (AVR Options) <-msplit-bit-shift>: Adjust doc.

2024-11-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/117814
	* config/arm/arm.cc (arm_attempt_dlstp_transform): Use
	reg_overlap_mentioned_p instead of rtx_equal_p to detect uses of
	vctp_vpr_generated inside subregs.

2024-11-29  Mariam Arutunian  <mariamarutunian@gmail.com>

	* expr.cc (gf2n_poly_long_div_quotient): New function.
	* expr.h (gf2n_poly_long_div_quotient):  New function declaration.
	* hwint.cc (reflect_hwi): New function.
	* hwint.h (reflect_hwi): New function declaration.
	* config/riscv/bitmanip.md (crc_rev<ANYI1:mode><ANYI:mode>4): New
	expander for reversed CRC.
	(crc<SUBX1:mode><SUBX:mode>4): New expander for bit-forward CRC.
	* config/riscv/iterators.md (SUBX1, ANYI1): New iterators.
	* config/riscv/riscv-protos.h (generate_reflecting_code_using_brev):
	New function declaration.
	(expand_crc_using_clmul): Likewise.
	(expand_reversed_crc_using_clmul): Likewise.
	* config/riscv/riscv.cc (generate_reflecting_code_using_brev): New
	function.
	(expand_crc_using_clmul): Likewise.
	(expand_reversed_crc_using_clmul): Likewise.
	* config/riscv/riscv.md (UNSPEC_CRC, UNSPEC_CRC_REV):  New unspecs.
	* doc/sourcebuild.texi: Document new target selectors.

2024-11-29  yulong  <shiyulong@iscas.ac.cn>

	* config.gcc: Add new SiFive *.o files.
	* config/riscv/generic-vector-ooo.md: New reservation.
	* config/riscv/genrvv-type-indexer.cc (main): New type.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vqmacc_def): New function.
	(SHAPE): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QMACC_OPS): New macros type.
	(vint32m1_t): Ditto.
	(vint32m2_t): Ditto.
	(vint32m4_t): Ditto.
	(vint32m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_QMACC_OPS): New builtins def.
	(DEF_RVV_TYPE_INDEX): Ditto.
	(DEF_RVV_FUNCTION): Ditto.
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX): New types def.
	(4x8x4): New op type.
	(2x8x2): Ditto.
	(quad_emul_vector): New base type.
	(quad_emul_signed_vector): Ditto.
	(quad_emul_unsigned_vector): Ditto.
	(quad_fixed_vector): Ditto.
	(quad_fixed_signed_vector): Ditto.
	(quad_fixed_unsigned_vector): Ditto.
	(quad_lmul1_vector): Ditto.
	(quad_lmul1_signed_vector): Ditto.
	(quad_lmul1_unsigned_vector): Ditto.
	* config/riscv/riscv-vector-builtins.h (enum required_ext): New extensions.
	(required_ext_to_isa_name): Ditto.
	(required_extensions_specified): Ditto.
	(struct function_group_info): Ditto.
	* config/riscv/riscv.md: New attr.
	* config/riscv/t-riscv: Add include for SiFive files.
	* config/riscv/vector-iterators.md: New iterator.
	* config/riscv/vector.md: New include for SiFive file.
	* config/riscv/sifive-vector-builtins-bases.cc: New file.
	* config/riscv/sifive-vector-builtins-bases.h: New file.
	* config/riscv/sifive-vector-builtins-functions.def: New file.
	* config/riscv/sifive-vector.md: New file.

2024-11-29  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-errata.h (TARGET_SUPPRESS_OPT_SPEC,
	TARGET_TURN_OFF_OPT_SPEC, CA53_ERR_835769_COMPILE_SPEC,
	CA53_ERR_843419_COMPILE_SPEC): New.
	(CA53_ERR_835769_SPEC, CA53_ERR_843419_SPEC): Use them.
	* config/aarch64/aarch64-elf-raw.h (CC1_SPEC, CC1PLUS_SPEC): Add
	AARCH64_ERRATA_COMPILE_SPEC.
	* config/aarch64/aarch64-freebsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
	* config/aarch64/aarch64-gnu.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
	* config/aarch64/aarch64-linux.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
	* config/aarch64/aarch64-netbsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
	* common/config/aarch64/aarch64-common.cc
	(is_host_cpu_not_armv8_base): New.
	* config/aarch64/driver-aarch64.cc: Remove extra newline
	* config/aarch64/aarch64.h (is_host_cpu_not_armv8_base): New.
	(MCPU_TO_MARCH_SPEC_FUNCTIONS): Add is_local_not_armv8_base.
	(EXTRA_SPEC_FUNCTIONS): Add is_local_cpu_armv8_base.
	* doc/invoke.texi: Document it.

2024-11-29  Richard Sandiford  <richard.sandiford@arm.com>

	* config/aarch64/aarch64-sme.md: In the section comments, add the
	architecture requirements alongside some mnemonics.
	* config/aarch64/aarch64-sve2.md: Likewise.

2024-11-29  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>

	* config/aarch64/aarch64-option-extensions.def
	(fp8dot4, ssve-fp8dot4): Add new extensions.
	(fp8dot2, ssve-fp8dot2): Likewise.
	* config/aarch64/aarch64-sve-builtins-base.cc (svdot_impl): Support fp8.
	(svdotprod_lane_impl): Likewise.
	(svdot_lane): Provide an unspec for fp8 types.
	* config/aarch64/aarch64-sve-builtins-shapes.cc
	(ternary_mfloat8_def): Add new class.
	(ternary_mfloat8): Add new shape.
	(ternary_mfloat8_lane_group_selection_def): Add new class.
	(ternary_mfloat8_lane_group_selection): Add new shape.
	* config/aarch64/aarch64-sve-builtins-shapes.h
	(ternary_mfloat8, ternary_mfloat8_lane_group_selection): Declare.
	* config/aarch64/aarch64-sve-builtins-sve2.def
	(svdot, svdot_lane): Add new DEF_SVE_FUNCTION_GS_FPM, twice to deal
	with the combination of features providing support for 32 and 16 bit
	floating point.
	* config/aarch64/aarch64-sve2.md (@aarch64_sve_dot<mode>): Add new.
	(@aarch64_sve_dot_lane<mode>): Likewise.
	* config/aarch64/aarch64.h:
	(TARGET_FP8DOT4, TARGET_SSVE_FP8DOT4): Add new defines.
	(TARGET_FP8DOT2, TARGET_SSVE_FP8DOT2): Likewise.
	* config/aarch64/iterators.md
	(UNSPEC_DOT_FP8, UNSPEC_DOT_LANE_FP8): Add new unspecs.
	* doc/invoke.texi: Document fp8dot4, fp8dot2, ssve-fp8dot4, ssve-fp8dot2
	extensions.

2024-11-29  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>

	* config/aarch64/aarch64-option-extensions.def
	(fp8fma, ssve-fp8fma): Add new options.
	* config/aarch64/aarch64-sve-builtins-functions.h
	(unspec_based_function_base): Add unspec_for_mfp8.
	(unspec_for): Return unspec_for_mfp8 on fpm-using cases.
	(sme_1mode_function): Fix call to parent ctor.
	(sme_2mode_function_t): Likewise.
	(unspec_based_mla_function, unspec_based_mla_lane_function): Handle
	fpm-using cases.
	* config/aarch64/aarch64-sve-builtins-shapes.cc
	(parse_element_type): Treat M as TYPE_SUFFIX_mf8
	(ternary_mfloat8_lane_def): Add new class.
	(ternary_mfloat8_opt_n_def): Likewise.
	(ternary_mfloat8_lane): Add new shape.
	(ternary_mfloat8_opt_n): Likewise.
	* config/aarch64/aarch64-sve-builtins-shapes.h
	(ternary_mfloat8_lane, ternary_mfloat8_opt_n): Declare.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(svmlalb_lane, svmlalb, svmlalt_lane, svmlalt): Update definitions
	with mfloat8_t unspec in ctor.
	(svmlallbb_lane, svmlallbb, svmlallbt_lane, svmlallbt, svmlalltb_lane,
	svmlalltb, svmlalltt_lane, svmlalltt, svmlal_impl): Add new FUNCTIONs.
	(svqrshr, svqrshrn, svqrshru, svqrshrun): Update definitions with
	nop mfloat8 unspec in ctor.
	* config/aarch64/aarch64-sve-builtins-sve2.def
	(svmlalb, svmlalt, svmlalb_lane, svmlalt_lane, svmlallbb, svmlallbt,
	svmlalltb, svmlalltt, svmlalltt_lane, svmlallbb_lane, svmlallbt_lane,
	svmlalltb_lane): Add new DEF_SVE_FUNCTION_GS_FPMs.
	* config/aarch64/aarch64-sve-builtins-sve2.h
	(svmlallbb_lane, svmlallbb, svmlallbt_lane, svmlallbt, svmlalltb_lane,
	svmlalltb, svmlalltt_lane, svmlalltt): Declare.
	* config/aarch64/aarch64-sve-builtins.cc
	(TYPES_h_float_mf8, TYPES_s_float_mf8): Add new types.
	(h_float_mf8, s_float_mf8): Add new SVE_TYPES_ARRAY.
	* config/aarch64/aarch64-sve2.md
	(@aarch64_sve_add_<sve2_fp8_fma_op_vnx8hf><mode>): Add new.
	(@aarch64_sve_add_<sve2_fp8_fma_op_vnx4sf><mode>): Add new.
	(@aarch64_sve_add_lane_<sve2_fp8_fma_op_vnx8hf><mode>): Likewise.
	(@aarch64_sve_add_lane_<sve2_fp8_fma_op_vnx4sf><mode>): Likewise.
	* config/aarch64/aarch64.h
	(TARGET_FP8FMA, TARGET_SSVE_FP8FMA): Likewise.
	* config/aarch64/iterators.md
	(VNx8HF_ONLY): Add new.
	(UNSPEC_FMLALB_FP8, UNSPEC_FMLALLBB_FP8, UNSPEC_FMLALLBT_FP8,
	UNSPEC_FMLALLTB_FP8, UNSPEC_FMLALLTT_FP8, UNSPEC_FMLALT_FP8): Likewise.
	(SVE2_FP8_TERNARY_VNX8HF, SVE2_FP8_TERNARY_VNX4SF): Likewise.
	(SVE2_FP8_TERNARY_LANE_VNX8HF, SVE2_FP8_TERNARY_LANE_VNX4SF): Likewise.
	(sve2_fp8_fma_op_vnx8hf, sve2_fp8_fma_op_vnx4sf): Likewise.
	* doc/invoke.texi: Document fp8fma and sve-fp8fma extensions.

2024-11-29  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>

	* config/aarch64/aarch64-sve-builtins-shapes.cc
	(parse_signature): Add an fpm_t (uint64_t) argument to functions that
	set the fpm register.
	(unary_convertxn_narrowt_def): New class.
	(unary_convertxn_narrowt): New shape.
	(unary_convertxn_narrow_def): New class.
	(unary_convertxn_narrow): New shape.
	* config/aarch64/aarch64-sve-builtins-shapes.h
	(unary_convertxn_narrowt): Declare.
	(unary_convertxn_narrow): Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(svcvt_fp8_impl): New class.
	(svcvtn_impl): Handle fp8 cases.
	(svcvt1, svcvt2, svcvtlt1, svcvtlt2): Add new FUNCTION.
	(svcvtnb): Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.def
	(svcvt1, svcvt2, svcvtlt1, svcvtlt2): Add new DEF_SVE_FUNCTION_GS_FPM.
	(svcvtn): Likewise.
	(svcvtnb, svcvtnt): Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.h
	(svcvt1, svcvt2, svcvtlt1, svcvtlt2, svcvtnb, svcvtnt): Declare.
	* config/aarch64/aarch64-sve-builtins.cc
	(TYPES_cvt_mf8, TYPES_cvtn_mf8, TYPES_cvtnx_mf8): Add new types arrays.
	(function_builder::get_name): Append _fpm to functions that set fpmr.
	(function_resolver::check_gp_argument): Deal with the fpm_t argument.
	(function_expander::expand): Set the fpm register before
	calling the insn if the function warrants it.
	* config/aarch64/aarch64-sve2.md (@aarch64_sve2_fp8_cvt): Add new.
	(@aarch64_sve2_fp8_cvtn): Likewise.
	(@aarch64_sve2_fp8_cvtnb): Likewise.
	(@aarch64_sve_cvtnt): Likewise.
	* config/aarch64/aarch64.h (TARGET_SSVE_FP8): Add new.
	* config/aarch64/iterators.md
	(VNx8SF_ONLY, SVE_FULL_HFx2): New mode iterators.
	(UNSPEC_F1CVT, UNSPEC_F1CVTLT, UNSPEC_F2CVT, UNSPEC_F2CVTLT): Add new.
	(UNSPEC_FCVTNB, UNSPEC_FCVTNT): Likewise.
	(UNSPEC_FP8FCVTN): Likewise.
	(FP8CVT_UNS, fp8_cvt_uns_op): Likewise.

2024-11-29  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>

	* config/aarch64/aarch64-sve-builtins-base.cc
	(svdiv_impl): Specify FPM_unused when folding.
	(svmul_impl): Likewise.
	* config/aarch64/aarch64-sve-builtins-shapes.cc
	(build_one): Use the group fpm_mode when creating function instances.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(svaba_impl, svqrshl_impl, svqshl_impl,svrshl_impl, svsra_impl):
	Specify FPM_unused when folding.
	* config/aarch64/aarch64-sve-builtins.cc (function_groups): Set
	fpm_mode on all elements.
	(neon_sve_function_groups, sme_function_groups): Likewise.
	(function_instance::hash): Include fpm_mode in hash.
	(function_builder::add_overloaded_functions): Use the group fpm mode.
	(function_resolver::lookup_form): Use the function instance fpm_mode
	when looking up a function.
	* config/aarch64/aarch64-sve-builtins.def
	(DEF_SVE_FUNCTION_GS_FPM): add define.
	(DEF_SVE_FUNCTION_GS): redefine against DEF_SVE_FUNCTION_GS_FPM.
	* config/aarch64/aarch64-sve-builtins.h (fpm_mode_index): New.
	(function_group_info): Add fpm_mode.
	(function_instance): Likewise.
	(function_instance::operator==): Handle fpm_mode.

2024-11-29  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>

	* config/aarch64/aarch64-sve-builtins.cc (TYPES_b_data): Add mf8.
	(TYPES_reinterpret1, TYPES_reinterpret): Likewise.
	* config/aarch64/aarch64-sve-builtins.def (svmfloat8_t): New type.
	(mf8): New type suffix.
	* config/aarch64/aarch64-sve-builtins.h (TYPE_mfloat): New
	type_class_index.

2024-11-29  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/115438
	* tree-vect-loop.cc (vect_transform_cycle_phi): For SLP also
	try to do the reduction adjustment by the initial value
	in the epilogue.

2024-11-29  Tejas Belagod  <tejas.belagod@arm.com>

	* tree.cc (build_vector_from_ctor): Add support to construct VLA vector
	constants from init constructors.

2024-11-29  Tejas Belagod  <tejas.belagod@arm.com>

	* gimple-fold.cc (maybe_canonicalize_mem_ref_addr): Handle variable
	sized vector types in BIT_FIELD_REF canonicalization.
	* tree-cfg.cc (verify_types_in_gimple_reference): Change object-size-
	checking for BIT_FIELD_REF to error offsets that are known_gt to be
	outside object-size.  Out-of-range offsets can happen in the case of
	indices that reference VLA SVE vector elements that may be outside the
	minimum vector size range and therefore maybe_gt is not appropirate
	here.

2024-11-29  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Flip
	TYPE_INDIVISBLE flag for SVE ACLE vector types.

2024-11-29  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
	__ARM_FEATURE_SVE_VECTOR_OPERATORS.

2024-11-29  Yury Khrustalev  <yury.khrustalev@arm.com>

	* config/aarch64/arm_acle.h (_CHKFEAT_GCS): New.

2024-11-29  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/117065
	* gimple-fold.cc (type_has_padding_at_level_p) <case UNION_TYPE>:
	Also continue if f has error_mark_node type.

2024-11-29  Jakub Jelinek  <jakub@redhat.com>

	PR target/117608
	* doc/extend.texi (__builtin_prefetch): Document that second
	argument may be also 2 and its meaning.
	* config/i386/i386.md (prefetch): Remove unreachable code.
	Clear write set operands[1] to const0_rtx if !TARGET_MOVRS or
	of locality is not 1.  Formatting fixes.
	* config/i386/i386-expand.cc (ix86_expand_builtin): Use IN_RANGE.
	Call gen_prefetch even for TARGET_MOVRS.
	* config/alpha/alpha.md (prefetch): Treat read_or_write 2 like 0.
	* config/mips/mips.md (prefetch): Likewise.
	* config/arc/arc.md (prefetch_1, prefetch_2, prefetch_3): Likewise.
	* config/riscv/riscv.md (prefetch): Likewise.
	* config/loongarch/loongarch.md (prefetch): Likewise.
	* config/sparc/sparc.md (prefetch): Likewise.  Use IN_RANGE.
	* config/ia64/ia64.md (prefetch): Likewise.
	* config/pa/pa.md (prefetch): Likewise.
	* config/aarch64/aarch64.md (prefetch): Likewise.
	* config/rs6000/rs6000.md (prefetch): Likewise.

2024-11-29  Alexandre Oliva  <oliva@adacore.com>

	PR tree-optimization/117723
	* tree-ssa-ifcombine.cc (tree_ssa_ifcombine_bb): Record
	forwarder blocks in path to exit, and stick to them.  Avoid
	computing the exit if obviously not needed, and if that
	enables additional optimizations.
	(tree_ssa_ifcombine_bb_1): Fix typos.

2024-11-28  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (*<any_shift:insn><mode>3_mask): Macroize
	pattern from *ashl<mode>3_mask and *<any_shiftrt:insn><mode>3_mask
	using any_shift code iterator.
	(*<any_shift:insn><mode>3_mask_1): Macroize pattern
	from *ashl<mode>3_mask_1 and *<any_shiftrt:insn><mode>3_mask_1
	using any_shift code iterator.
	(*<any_shift:insn><mode>3_add): Macroize pattern
	from *ashl<mode>3_add and *<any_shiftrt:insn><mode>3_add
	using any_shift code iterator.
	(*<any_shift:insn><mode>3_add_1): Macroize pattern
	from *ashl<mode>3_add_1 and *<any_shiftrt:insn><mode>3_add_1
	using any_shift code iterator.
	(*<insn><mode>3_sub): Macroize pattern
	from *ashl<mode>3_sub and *<any_shiftrt:insn><mode>3_sub
	using any_shift code iterator.
	(*<any_shift:insn><mode>3_sub_1): Macroize pattern
	from *ashl<mode>3_sub_1 and *<any_shiftrt:insn><mode>3_sub_1
	using any_shift code iterator.

2024-11-28  Mariam Arutunian  <mariamarutunian@gmail.com>

	* builtin-types.def (BT_FN_UINT8_UINT8_UINT8_CONST_SIZE): Define.
	(BT_FN_UINT16_UINT16_UINT8_CONST_SIZE): Likewise.
	(BT_FN_UINT16_UINT16_UINT16_CONST_SIZE): Likewise.
	(BT_FN_UINT32_UINT32_UINT8_CONST_SIZE): Likewise.
	(BT_FN_UINT32_UINT32_UINT16_CONST_SIZE): Likewise.
	(BT_FN_UINT32_UINT32_UINT32_CONST_SIZE): Likewise.
	(BT_FN_UINT64_UINT64_UINT8_CONST_SIZE): Likewise.
	(BT_FN_UINT64_UINT64_UINT16_CONST_SIZE): Likewise.
	(BT_FN_UINT64_UINT64_UINT32_CONST_SIZE): Likewise.
	(BT_FN_UINT64_UINT64_UINT64_CONST_SIZE): Likewise.
	* builtins.cc (associated_internal_fn): Handle CRC related builtins.
	(expand_builtin_crc_table_based): New function.
	(expand_builtin): Handle CRC related builtins.
	* builtins.def (BUILT_IN_CRC8_DATA8): New builtin.
	(BUILT_IN_CRC16_DATA8): Likewise.
	(BUILT_IN_CRC16_DATA16): Likewise.
	(BUILT_IN_CRC32_DATA8): Likewise.
	(BUILT_IN_CRC32_DATA16): Likewise.
	(BUILT_IN_CRC32_DATA32): Likewise.
	(BUILT_IN_CRC64_DATA8): Likewise.
	(BUILT_IN_CRC64_DATA16): Likewise.
	(BUILT_IN_CRC64_DATA32): Likewise.
	(BUILT_IN_CRC64_DATA64): Likewise.
	(BUILT_IN_REV_CRC8_DATA8): New builtin.
	(BUILT_IN_REV_CRC16_DATA8): Likewise.
	(BUILT_IN_REV_CRC16_DATA16): Likewise.
	(BUILT_IN_REV_CRC32_DATA8): Likewise.
	(BUILT_IN_REV_CRC32_DATA16): Likewise.
	(BUILT_IN_REV_CRC32_DATA32): Likewise.
	(BUILT_IN_REV_CRC64_DATA8): Likewise.
	(BUILT_IN_REV_CRC64_DATA16): Likewise.
	(BUILT_IN_REV_CRC64_DATA32): Likewise.
	(BUILT_IN_REV_CRC64_DATA64): Likewise.
	* builtins.h (expand_builtin_crc_table_based): New function
	declaration.
	* doc/extend.texi: Add documentation for new CRC builtins.

2024-11-28  Mariam Arutunian  <mariamarutunian@gmail.com>

	* doc/md.texi (crc@var{m}@var{n}4, crc_rev@var{m}@var{n}4): Document.
	* expr.cc (calculate_crc): New function.
	(assemble_crc_table): Likewise.
	(generate_crc_table): Likewise.
	(calculate_table_based_CRC): Likewise.
	(expand_crc_table_based): Likewise.
	(gen_common_operation_to_reflect): Likewise.
	(reflect_64_bit_value): Likewise.
	(reflect_32_bit_value): Likewise.
	(reflect_16_bit_value): Likewise.
	(reflect_8_bit_value): Likewise.
	(generate_reflecting_code_standard): Likewise.
	(expand_reversed_crc_table_based): Likewise.
	* expr.h (generate_reflecting_code_standard): New function declaration.
	(expand_crc_table_based): Likewise.
	(expand_reversed_crc_table_based): Likewise.
	* internal-fn.cc: (crc_direct): Define.
	(direct_crc_optab_supported_p): Likewise.
	(expand_crc_optab_fn): New function
	* internal-fn.def (CRC, CRC_REV): New internal functions.
	* optabs.def (crc_optab, crc_rev_optab): New optabs.
	Signed-off-by: Mariam Arutunian <mariamarutunian@gmail.com>
	Co-authored-by: Joern Rennecke <joern.rennecke@embecosm.com>
	Co-authored-by: Jeff Law <jlaw@ventanamicro.com>

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR target/117642
	* doc/extend.texi: Remove documentation of warning for unimplemented
	__sync_* operations, such warning has never been implemented.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR c/117023
	* gimple-range-infer.cc (gimple_infer_range::gimple_infer_range):
	Handle also nonnull_if_nonzero attributes.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR c/117023
	* gimple.h (infer_nonnull_range_by_attribute): Add a tree *
	argument defaulted to NULL.
	* gimple.cc (infer_nonnull_range_by_attribute): Add op2 argument.
	Handle also nonnull_if_nonzero attributes.
	* tree.cc (get_nonnull_args): Fix comment typo.
	* builtins.cc (validate_arglist): Handle nonnull_if_nonzero attribute.
	* tree-ssa-ccp.cc (pass_post_ipa_warn::execute): Handle
	nonnull_if_nonzero attributes.
	* ubsan.cc (instrument_nonnull_arg): Adjust
	infer_nonnull_range_by_attribute caller.  If it returned true and
	filed in non-NULL arg2, check that arg2 is non-zero as another
	condition next to checking that arg is zero.
	* doc/extend.texi (nonnull_if_nonzero): Document new attribute.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	* config/rs6000/rs6000.h (struct machine_function): Add
	asm_redzone_clobber_seen member.
	* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Force
	info->push_p if cfun->machine->asm_redzone_clobber_seen.
	* config/rs6000/rs6000.cc (TARGET_REDZONE_CLOBBER): Redefine.
	(rs6000_redzone_clobber): New function.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	* target.def (redzone_clobber): New target hook.
	* varasm.cc (decode_reg_name_and_count): Return -5 for
	"redzone".
	* cfgexpand.cc (expand_asm_stmt): Handle redzone clobber.
	* config/i386/i386.h (struct machine_function): Add
	asm_redzone_clobber_seen member.
	* config/i386/i386.cc (ix86_compute_frame_layout): Don't
	use red zone if cfun->machine->asm_redzone_clobber_seen.
	(ix86_redzone_clobber): New function.
	(TARGET_REDZONE_CLOBBER): Redefine.
	* doc/extend.texi (Clobbers and Scratch Registers): Document
	the "redzone" clobber.
	* doc/tm.texi.in: Add @hook TARGET_REDZONE_CLOBBER.
	* doc/tm.texi: Regenerate.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR c++/116416
	* flag-types.h (enum zero_init_padding_bits_kind): New type.
	* tree.h (CONSTRUCTOR_ZERO_PADDING_BITS): Define.
	* common.opt (fzero-init-padding-bits=): New option.
	* expr.cc (categorize_ctor_elements_1): Handle
	CONSTRUCTOR_ZERO_PADDING_BITS or
	flag_zero_init_padding_bits == ZERO_INIT_PADDING_BITS_ALL.  Fix
	up *p_complete = -1; setting for unions.
	(complete_ctor_at_level_p): Handle unions differently for
	flag_zero_init_padding_bits == ZERO_INIT_PADDING_BITS_STANDARD.
	* gimple-fold.cc (type_has_padding_at_level_p): Fix up UNION_TYPE
	handling, return also true for UNION_TYPE with no FIELD_DECLs
	and non-zero size, handle QUAL_UNION_TYPE like UNION_TYPE.
	* doc/invoke.texi (-fzero-init-padding-bits=@var{value}): Document.

2024-11-28  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/117557
	* tree-vect-stmts.cc (vectorizable_store): Flatten the ncopies and
	vec_num loops.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/117358
	* gimple-fold.cc (gimple_fold_builtin_memory_op): Punt if stmt has no
	vdef in ssa form.
	(gimple_fold_builtin_bcmp): Punt if stmt has no vuse in ssa form.
	(gimple_fold_builtin_bcopy): Punt if stmt has no vdef in ssa form.
	(gimple_fold_builtin_bzero): Likewise.
	(gimple_fold_builtin_memset): Likewise.  Use return false instead of
	return NULL_TREE.
	(gimple_fold_builtin_strcpy): Punt if stmt has no vdef in ssa form.
	(gimple_fold_builtin_strncpy): Likewise.
	(gimple_fold_builtin_strchr): Punt if stmt has no vuse in ssa form.
	(gimple_fold_builtin_strstr): Likewise.
	(gimple_fold_builtin_strcat): Punt if stmt has no vdef in ssa form.
	(gimple_fold_builtin_strcat_chk): Likewise.
	(gimple_fold_builtin_strncat): Likewise.
	(gimple_fold_builtin_strncat_chk): Likewise.
	(gimple_fold_builtin_string_compare): Likewise.
	(gimple_fold_builtin_fputs): Likewise.
	(gimple_fold_builtin_memory_chk): Likewise.
	(gimple_fold_builtin_stxcpy_chk): Likewise.
	(gimple_fold_builtin_stxncpy_chk): Likewise.
	(gimple_fold_builtin_stpcpy): Likewise.
	(gimple_fold_builtin_snprintf_chk): Likewise.
	(gimple_fold_builtin_sprintf_chk): Likewise.
	(gimple_fold_builtin_sprintf): Likewise.
	(gimple_fold_builtin_snprintf): Likewise.
	(gimple_fold_builtin_fprintf): Likewise.
	(gimple_fold_builtin_printf): Likewise.
	(gimple_fold_builtin_realloc): Likewise.

2024-11-28  Jakub Jelinek  <jakub@redhat.com>

	PR c/117802
	* builtins.cc (fold_builtin_iseqsig): Handle BITINT_TYPE like
	INTEGER_TYPE.

2024-11-28  David Malcolm  <dmalcolm@redhat.com>

	* timevar.cc: Include "make-unique.h".
	(timer::named_items::make_json): Convert return type to unique_ptr.
	Avoid naked "new".
	(make_json_for_timevar_time_def): Likewise.
	(timer::timevar_def::make_json): Likewise.
	(timer::make_json): Likewise.
	* timevar.h (timer::make_json): Likewise.
	(timer::timevar_def::make_json): Likewise.
	* tree-diagnostic-client-data-hooks.cc: Update for above changes.

2024-11-28  David Malcolm  <dmalcolm@redhat.com>

	PR c/104896
	* common/config/ia64/ia64-common.cc (ia64_handle_option): Replace
	"%<%s%>" with "%qs" in message wording.
	* common/config/rs6000/rs6000-common.cc (rs6000_handle_option):
	Likewise.
	* config/aarch64/aarch64.cc (aarch64_validate_sls_mitigation):
	Likewise.
	(aarch64_override_options): Likewise.
	(aarch64_process_target_attr): Likewise.
	* config/arm/aarch-common.cc (aarch_validate_mbranch_protection):
	Likewise.
	* config/pru/pru.cc (pru_insert_attributes): Likewise.
	* config/riscv/riscv-target-attr.cc
	(riscv_target_attr_parser::parse_arch): Likewise.
	* omp-general.cc (oacc_verify_routine_clauses): Likewise.
	* tree-ssa-uninit.cc (maybe_warn_read_write_only): Likewise.
	(maybe_warn_pass_by_reference): Likewise.

2024-11-27  Uros Bizjak  <ubizjak@gmail.com>

	PR target/36503
	* config/i386/i386.md (*ashl<mode>3_add):
	New define_insn_and_split pattern.
	(*ashl<mode>3_add_1): Ditto.
	(*<insn><mode>3_add): Ditto.
	(*<insn><mode>3_add_1): Ditto.
	(*ashl<mode>3_sub): Rename from *ashl<mode>3_negcnt.
	(*ashl<mode>3_sub_1): Rename from *ashl<mode>3_negcnt_1.
	(*<insn><mode>3_sub): Rename from *<insn><mode>3_negcnt.
	(*<insn><mode>3_sub_1): Rename from *<insn><mode>3_negcnt_1.

2024-11-27  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/117776
	* match.pd (nested int casts): Allow for the case
	where the final prec is greater than the original
	prec.

2024-11-27  Pan Li  <pan2.li@intel.com>

	* match.pd: Refactor sorts of unsigned SAT_ADD match pattern for
	IFN ADD_OVERFLOW.

2024-11-27  Jakub Jelinek  <jakub@redhat.com>

	PR target/117642
	* builtins.cc (expand_builtin_sync_lock_release): Change return type
	from void to rtx, return result of expand_atomic_store.
	(expand_builtin) <case BUILT_IN_SYNC_LOCK_RELEASE_16>: If
	expand_builtin_sync_lock_release returns NULL, do a break rather
	than return const0_rtx.

2024-11-27  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/117692
	* tree.cc (get_range_pos_neg): Adjust function comment, use
	non-negative instead of positive.
	* match.pd
	(((X /[ex] C1) +- C2) * (C1 * C3) -> (X * C3) +- (C1 * C2 * C3)):
	Use casts to utype if type is signed, factor isn't 1 and
	C1 and C2 could have different sign for + or could have the
	same sign for -.

2024-11-27  Alexandre Oliva  <oliva@adacore.com>

	* tree-ssa-ifcombine.cc (ifcombine_ifandif): Avoid fallback
	conjunction of noncontiguous conditions.

2024-11-27  Florian Weimer  <fweimer@redhat.com>