[APX EGPR] Add backend hook for base_reg_class/index_reg_class.

Add backend helper functions to verify if a rtx_insn can adopt EGPR to
its base/index reg of memory operand. The verification rule goes like
  1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32.
  2. Disable EGPR for unrecognized insn.
  3. If which_alternative is not decided, loop through enabled alternatives
  and check its attr_gpr32. Only enable EGPR when all enabled
  alternatives has attr_gpr32 = 1.
  4. If which_alternative is decided, enable/disable EGPR by its corresponding
  attr_gpr32.

gcc/ChangeLog:

	* config/i386/i386-protos.h (ix86_insn_base_reg_class): New
	prototype.
	(ix86_regno_ok_for_insn_base_p): Likewise.
	(ix86_insn_index_reg_class): Likewise.
	* config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
	New helper function to scan the insn.
	(ix86_insn_base_reg_class): New function to choose BASE_REG_CLASS.
	(ix86_regno_ok_for_insn_base_p): Likewise for base regno.
	(ix86_insn_index_reg_class): Likewise for INDEX_REG_CLASS.
	* config/i386/i386.h (INSN_BASE_REG_CLASS): Define.
	(REGNO_OK_FOR_INSN_BASE_P): Likewise.
	(INSN_INDEX_REG_CLASS): Likewise.
	(enum reg_class): Add INDEX_GPR16.
	(GENERAL_GPR16_REGNO_P): Define.
	* config/i386/i386.md (gpr32): New attribute.

Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>