RISC-V: Prohibit combination of 'E' and 'H'

According to the ratified privileged specification (version 20211203),
it says:

> The hypervisor extension depends on an "I" base integer ISA with 32 x
> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.

Also in the latest draft, it also prohibits RV64E with the 'H' extension.
This commit prohibits the combination of 'E' and 'H' extensions.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
	Prohibit 'E' and 'H' combinations.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-26.c: New test.