[Aarch64, Patch] Update failing testcase pr62178.c

This patch changes pr62178.c so that it now scans
for two `ldr`s, one into an `s` register, instead
of a `ld1r` as before. Also add a scan for an mla
instruction.

The `ld1r` was needed when this should have generated
a mla by vector. Now that we can generate an mla by
element instruction and can load directly into the
simd register, it is cheaper to not do the ld1r
which needlessly duplicates the single element used
across the whole vector register.

Committed on behalf of Jackson Woodruff

gcc/testsuite/

	* gcc.target/aarch64/pr62178.c: Updated testcase
	to scan for two ldrs and an mla.

From-SVN: r252086

gcc/testsuite/ChangeLog

+2017-09-13  Jackson Woodruff  <jackson.woodruff@arm.com>
+
+	* gcc.target/aarch64/pr62178.c: Updated testcase
+	to scan for two ldrs and an mla.
+
 2017-09-13  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/59949

gcc/testsuite/gcc.target/aarch64/pr62178.c

@@ -14,4 +14,6 @@ void foo (void) {
     }
 }
 
-/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\."} } */
+/* { dg-final { scan-assembler "ldr\\ts\[0-9\]+, \\\[x\[0-9\]+, \[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "ldr\\tq\[0-9\]+, \\\[x\[0-9\]+\\\], \[0-9\]+" } } */
+/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" } } */