RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

This patch would like to add testcases of the signed scalar SAT_ADD
for form 3.  Aka:

Form 3:
  #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)           \
  T __attribute__((noinline))                            \
  sat_s_add_##T##_fmt_3 (T x, T y)                       \
  {                                                      \
    T sum;                                               \
    bool overflow = __builtin_add_overflow (x, y, &sum); \
    return overflow ? x < 0 ? MIN : MAX : sum;           \
  }

DEF_SAT_S_ADD_FMT_3 (int64_t, uint64_t, INT64_MIN, INT64_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_s_add-10.c: New test.
	* gcc.target/riscv/sat_s_add-11.c: New test.
	* gcc.target/riscv/sat_s_add-12.c: New test.
	* gcc.target/riscv/sat_s_add-9.c: New test.
	* gcc.target/riscv/sat_s_add-run-10.c: New test.
	* gcc.target/riscv/sat_s_add-run-11.c: New test.
	* gcc.target/riscv/sat_s_add-run-12.c: New test.
	* gcc.target/riscv/sat_s_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>