RISC-V: Support FP SGNJX autovec for VLS mode

This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.

Give sample code as below:

void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
  for (int i = 0; i < 128; i++)
    out[i] = in1[i] * copysignf (1.0, in2[i]);
}

Before this patch:
test:
  li      a5,128
  vsetvli zero,a5,e32,m1,ta,ma
  vle32.v v2,0(a1)
  lui     a4,%hi(.LC0)
  flw     fa5,%lo(.LC0)(a4)
  vfmv.v.f        v1,fa5
  vle32.v v3,0(a2)
  vfsgnj.vv       v1,v1,v3
  vfmul.vv        v1,v1,v2
  vse32.v v1,0(a0)
  ret

After this patch:
test:
  li      a5,128
  vsetvli zero,a5,e32,m1,ta,ma
  vle32.v v1,0(a1)
  vle32.v v2,0(a2)
  vfsgnjx.vv      v1,v1,v2
  vse32.v v1,0(a0)
  ret

This SGNJX autovec acts on function call copysignf/copysignf
in math.h too. And it depends on the option -ffast-math.

gcc/ChangeLog:

	* config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>