rs6000: Add veqv support to *eqv<mode>3_internal1

When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version.  I think it
is an oversight, this patch is to consider veqv as well.

gcc/ChangeLog:

	* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
	insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.