Alpha: Permit constant zero source for "insvmisaligndi"

Eliminate a redundant bitwise inclusive OR operation on the insertion of
constant zero into a bit-field, improving code produced at `-O2' from an
output sequence such as:

	mov $31,$3				# Redundant!
	ldq_u $1,7($16)
	insqh $3,$16,$3				# Redundant!
	ldq_u $2,0($16)
	mskqh $1,$16,$1
	mskql $2,$16,$2
	bis $1,$3,$1				# Redundant!
	stq_u $1,7($16)
	stq_u $2,0($16)
	ret $31,($26),1

to:

	ldq_u $2,7($16)
	ldq_u $1,0($16)
	mskqh $2,$16,$2
	stq_u $2,7($16)
	mskql $1,$16,$1
	stq_u $1,0($16)
	ret $31,($26),1

for a quadword unaligned store operation.  As shown in the example this
only triggers for the high-part store (and therefore only for 2-byte,
4-byte, and 8-byte stores), because `insXl' insns are fully expressed in
terms of RTL and therefore the insertion of zero is eliminated in later
RTL passes, however corresponding `insXh' insns are unspecs only, making
them impossible to see through.

We can get this optimal right from expand though, given that our handler
for "insvmisaligndi", i.e. `alpha_expand_unaligned_store', has explicit
provisions for `const0_rtx' source.

	gcc/
	* config/alpha/alpha.md (insvmisaligndi): Use "reg_or_0_operand"
	rather than "register_operand" for operand 3.

	gcc/testsuite/
	* gcc.target/alpha/stlx0.c: New file.
	* gcc.target/alpha/stqx0.c: New file.
	* gcc.target/alpha/stwx0.c: New file.
	* gcc.target/alpha/stwx0-bwx.c: New file.