aarch64: Relax aarch64_<sur><addsub>hn2<mode> RTL pattern
Implement v[r]addhn2 and v[r]subhn2 Neon intrinsic RTL patterns using a vec_concat of a register_operand and an ADDSUBHN unspec - instead of just an ADDSUBHN2 unspec. This more relaxed pattern allows for more aggressive combinations and ultimately better code generation. This patch also removes the now redundant [R]ADDHN2 and [R]SUBHN2 unspecs and their iterator. gcc/ChangeLog: 2021-03-03 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>): Implement as an expand emitting a big/little endian instruction pattern. (aarch64_<sur><addsub>hn2<mode>_insn_le): Define. (aarch64_<sur><addsub>hn2<mode>_insn_be): Define. * config/aarch64/iterators.md: Remove UNSPEC_[R]ADDHN2 and UNSPEC_[R]SUBHN2 unspecs and ADDSUBHN2 iterator.
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