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For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv...
For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv can be used instead of avx512 mask. gcc/ChangeLog: PR target/100648 * config/i386/sse.md (*avx_cmp<mode>3_lt): New define_insn_and_split. (*avx_cmp<mode>3_ltint): Ditto. (*avx2_pcmp<mode>3_3): Ditto. (*avx2_pcmp<mode>3_4): Ditto. (*avx2_pcmp<mode>3_5): Ditto. gcc/testsuite/ChangeLog: PR target/100648 * g++.target/i386/avx2-pr54700-2.C: Adjust testcase. * g++.target/i386/avx512vl-pr54700-1a.C: New test. * g++.target/i386/avx512vl-pr54700-1b.C: New test. * g++.target/i386/avx512vl-pr54700-2a.C: New test. * g++.target/i386/avx512vl-pr54700-2b.C: New test. * gcc.target/i386/avx512vl-pr100648.c: New test. * gcc.target/i386/avx512vl-blendv-1.c: New test. * gcc.target/i386/avx512vl-blendv-2.c: New test.
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- gcc/config/i386/sse.md 152 additions, 0 deletionsgcc/config/i386/sse.md
- gcc/testsuite/g++.target/i386/avx2-pr54700-2.C 7 additions, 1 deletiongcc/testsuite/g++.target/i386/avx2-pr54700-2.C
- gcc/testsuite/g++.target/i386/avx512vl-pr54700-1a.C 9 additions, 0 deletionsgcc/testsuite/g++.target/i386/avx512vl-pr54700-1a.C
- gcc/testsuite/g++.target/i386/avx512vl-pr54700-1b.C 9 additions, 0 deletionsgcc/testsuite/g++.target/i386/avx512vl-pr54700-1b.C
- gcc/testsuite/g++.target/i386/avx512vl-pr54700-2a.C 17 additions, 0 deletionsgcc/testsuite/g++.target/i386/avx512vl-pr54700-2a.C
- gcc/testsuite/g++.target/i386/avx512vl-pr54700-2b.C 17 additions, 0 deletionsgcc/testsuite/g++.target/i386/avx512vl-pr54700-2b.C
- gcc/testsuite/gcc.target/i386/avx512vl-blendv-1.c 51 additions, 0 deletionsgcc/testsuite/gcc.target/i386/avx512vl-blendv-1.c
- gcc/testsuite/gcc.target/i386/avx512vl-blendv-2.c 41 additions, 0 deletionsgcc/testsuite/gcc.target/i386/avx512vl-blendv-2.c
- gcc/testsuite/gcc.target/i386/avx512vl-pr100648.c 21 additions, 0 deletionsgcc/testsuite/gcc.target/i386/avx512vl-pr100648.c
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