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Commit 4bd3ccae authored by Robin Dapp's avatar Robin Dapp
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RISC-V: testsuite: Fix SELECT_VL SLP fallout. 

This fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we allow
SLP with SELECT_VL.

Assisted by sed and regtested on rv64gcv_zvfh_zvbb.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Expect
	length-controlled loop.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
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gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_s_add_int8_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_s_add_int16_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_s_add_int32_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_s_add_int64_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint8_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint16_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint32_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint64_t_fmt_3:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint8_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint16_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint32_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint64_t_fmt_4:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint8_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint16_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint32_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint16_t_fmt_1:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint64_t_fmt_5:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint8_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint16_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+ 1
− 1
View file @ 4bd3ccae
......@@ -8,7 +8,7 @@
/*
** vec_sat_u_add_uint32_t_fmt_6:
** ...
** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
** ...
** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** ...
......
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