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AArch64: Fix vector re-interpretation between partial SIMD modes
While writing a patch series I started getting incorrect codegen out from VEC_PERM on partial struct types. It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS implementation has a slight bug in it. The hook only checked for SIMD to Partial but never Partial to SIMD. This resulted in incorrect subregs to be generated from the fallback code in VEC_PERM_EXPR expansions. I have unfortunately not been able to trigger it using a standalone testcase as the mid-end optimizes away the permute every time I try to describe a permute that would result in the bug. The patch now rejects any conversion of partial SIMD struct types, unless they are both partial structures of the same number of registers or one is a SIMD type who's size is less than 8 bytes. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_can_change_mode_class): Restrict conversions between partial struct types properly.
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