RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
SEW=16 for below instructions

vfwcvt.f.f.v
vfncvt.f.f.w

Then users can leverage the instrinsic APIs to perform the conversion
between RVV vector single float point and half float point.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
	(vfloat32m1_t): Likewise.
	(vfloat32m2_t): Likewise.
	(vfloat32m4_t): Likewise.
	(vfloat32m8_t): Likewise.
	* config/riscv/riscv-vector-builtins.def: Fix typo in comments.
	* config/riscv/vector-iterators.md: Add single to half machine
	mode conversion.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.