RISC-V: Fix the illegal operands for the XTheadMemidx extension.

The pattern "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip" and
"*zero_extendhi<GPR:mode>2_bitmanip" in bitmanip.md are similar
to the pattern "*th_memidx_bb_extendqi<SUPERQI:mode>2" and
"*th_memidx_bb_zero_extendhi<GPR:mode>2" in thead.md, which will
cause the wrong instruction to be generated and report the
following error in binutils:
Assembler messages:
Error: illegal operands `lb a5,(a0),1,0'

In fact, the correct instruction is "th.lbia a5,(a0),1,0".

gcc/ChangeLog:

	* config/riscv/bitmanip.md: Avoid the conflict between
	zbb and xtheadmemidx in patterns.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmemidx-uindex-zbb.c: New test.