AArch64: Set L1 data cache size according to size on CPUs

This sets the L1 data cache size for some cores based on their size in their
Technical Reference Manuals.

Today the port minimum is 256 bytes as explained in commit
g:9a99559a, however like Neoverse V2 most cores
actually define the L1 cache size as 64-bytes.  The generic Armv9-A model was
already changed in g:f000cb8c and this
change follows suite for a few other cores based on their TRMs.

This results in less memory pressure when running on large core count machines.

gcc/ChangeLog:

	* config/aarch64/tuning_models/cortexx925.h: Set L1 cache size to 64b.
	* config/aarch64/tuning_models/neoverse512tvb.h: Likewise.
	* config/aarch64/tuning_models/neoversen1.h: Likewise.
	* config/aarch64/tuning_models/neoversen2.h: Likewise.
	* config/aarch64/tuning_models/neoversen3.h: Likewise.
	* config/aarch64/tuning_models/neoversev1.h: Likewise.
	* config/aarch64/tuning_models/neoversev2.h: Likewise.
	(neoversev2_prefetch_tune): Removed.
	* config/aarch64/tuning_models/neoversev3.h: Likewise.
	* config/aarch64/tuning_models/neoversev3ae.h: Likewise.