RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API

This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:

vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin vfmax
vfsgnj vfsgnjn vfsgnjx
vmfeq vmfne vmflt vmfle vmfgt vmfge
vfclass vfmerge
vfmv
vfcvt vfwcvt vfncvt

Then users can leverage the instrinsic APIs to perform the FP=16 related
operations. Please note not all the instrinsic APIs are coverred in the
test files, only pick some typical ones due to too many. We will perform
the FP16 related instrinsic API test entirely soon.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
	(vfloat32m1_t): Ditto.
	(vfloat32m2_t): Ditto.
	(vfloat32m4_t): Ditto.
	(vfloat32m8_t): Ditto.
	(vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
	(vint16mf2_t): Ditto.
	(vint16m1_t): Ditto.
	(vint16m2_t): Ditto.
	(vint16m4_t): Ditto.
	(vint16m8_t): Ditto.
	(vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
	(vuint16mf2_t): Ditto.
	(vuint16m1_t): Ditto.
	(vuint16m2_t): Ditto.
	(vuint16m4_t): Ditto.
	(vuint16m8_t): Ditto.
	(vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
	(vint32m1_t): Ditto.
	(vint32m2_t): Ditto.
	(vint32m4_t): Ditto.
	(vint32m8_t): Ditto.
	(vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	* config/riscv/vector-iterators.md: Add FP=16 support for V,
	VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>