RISC-V: Fix misaligned stack offset for interrupt function

`interrupt` function will backup fcsr register, but it fixed to SImode,
it's not big issue since fcsr only used 8 bits so far, however the
offset should still using UNITS_PER_WORD to prevent the stack offset
become non 8 byte aligned, it will cause problem for RV64.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
	offset of fcsr.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/interrupt-misaligned.c: New.