RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API

This patch support the intrinsic API of FP16 ZVFH Reduction floating-point.
Aka SEW=16 for below instructions:

vfredosum vfredusum
vfredmax vfredmin
vfwredosum vfwredusum

Then users can leverage the instrinsic APIs to perform the FP=16 related
reduction operations. Please note not all the instrinsic APIs are coverred
in the test files, only pick some typical ones due to too many. We will
perform the FP16 related instrinsic API test entirely soon.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat16mf4_t): Add vfloat16mf4_t to WF operations.
	(vfloat16mf2_t): Likewise.
	(vfloat16m1_t): Likewise.
	(vfloat16m2_t): Likewise.
	(vfloat16m4_t): Likewise.
	(vfloat16m8_t): Likewise.
	* config/riscv/vector-iterators.md: Add FP=16 to VWF, VWF_ZVE64,
	VWLMUL1, VWLMUL1_ZVE64, vwlmul1 and vwlmul1_zve64.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Add new test cases.