AArch64: support encoding integer immediates using floating point moves

This patch extends our immediate SIMD generation cases to support generating
integer immediates using floating point operation if the integer immediate maps
to an exact FP value.

As an example:

uint32x4_t f1() {
    return vdupq_n_u32(0x3f800000);
}

currently generates:

f1:
        adrp    x0, .LC0
        ldr     q0, [x0, #:lo12:.LC0]
        ret

i.e. a load, but with this change:

f1:
        fmov    v0.4s, 1.0e+0
        ret

Such immediates are common in e.g. our Math routines in glibc because they are
created to extract or mark part of an FP immediate as masks.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_sve_valid_immediate,
	aarch64_simd_valid_immediate): Refactor accepting modes and values.
	(aarch64_float_const_representable_p): Refactor and extract FP checks
	into ...
	(aarch64_real_float_const_representable_p): ...This and fix fail
	fallback from real_to_integer.
	(aarch64_advsimd_valid_immediate): Use it.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/const_create_using_fmov.c: New test.