[committed] [RISC-V] Handle more cases in riscv_expand_conditional_move

As I've mentioned in the main zicond thread, Ventana has had patches
that support more cases by first emitting a suitable scc instruction
essentially as a canonicalization step of the condition for zicond.

For example if we have

(set (target) (if_then_else (op (reg1) (reg2))
                            (true_value)
                            (false_value)))

The two register comparison isn't handled by zicond directly.  But we
can generate something like this instead

(set (temp) (op (reg1) (reg2)))
(set (target) (if_then_else (op (temp) (const_int 0))
                            (true_value)
                            (false_value)

Then let the remaining code from Xiao handle the true_value/false_value
to make sure it's zicond compatible.

This is primarily Raphael's work.  My involvement has been mostly to
move it from its original location (in the .md file) into the expander
function and fix minor problems with the FP case.

gcc/
	* config/riscv/riscv.cc (riscv_expand_int_scc): Add invert_ptr
	as an argument and pass it to riscv_emit_int_order_test.
	(riscv_expand_conditional_move): Handle cases where the condition
	is not EQ/NE or the second argument to the conditional is not
	(const_int 0).
	* config/riscv/riscv-protos.h (riscv_expand_int_scc): Update prototype.

Co-authored-by: Jeff Law <jlaw@ventanamicro.com>