RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
	(vfloat16mf2_t): Likewise.
	(vfloat16m1_t): Likewise.
	(vfloat16m2_t): Likewise.
	(vfloat16m4_t): Likewise.
	(vfloat16m8_t): Likewise.
	* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
	* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
	to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
	* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
	vlmul and ratio.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/mov-14.c: New test.
	* gcc.target/riscv/rvv/base/spill-13.c: New test.