RISC-V: Add sifive-p450, sifive-p67 to -mcpu
gcc/ChangeLog: * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. * doc/invoke.texi (RISC-V Options): Add sifive-p450, sifive-p670. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-sifive-p450.c: New test. * gcc.target/riscv/mcpu-sifive-p670.c: New test.
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- gcc/config/riscv/riscv-cores.def 9 additions, 0 deletionsgcc/config/riscv/riscv-cores.def
- gcc/doc/invoke.texi 2 additions, 1 deletiongcc/doc/invoke.texi
- gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c 34 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
- gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
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