sparc.md (*cmp{si,di}_insn): %r0 -> %0.

	* sparc/sparc.md (*cmp{si,di}_insn): %r0 -> %0.
	(DFmode move split): Ensure registers not extended v9 fp regs.
	(*mov{sf,df,tf}_cc_reg_sp64): %r3 -> %3.

From-SVN: r11437