RISC-V: Add test cases for RVV FP16 vreinterpret

This patch would like to add more tests for RVV FP16 vreinterpret, aka

vfloat16*_t <==> v{u}int16*_t.

There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already.
It doesn't break anything in SPEC as there is no such vreinterpret insn.
From the user's perspective, it is reasonable to do some type convert
between vfloat16 and v{u}int16 when only ZVFHMIN is enabled.

This patch would like to add new test cases to make sure the RVV FP16
vreinterpret works well as expected.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new cases.
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Diito.