RISC-V: Fine tune merge operand constraint for integer/load/store

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Split indexed load
	patterns according to RVV ISA.
	* config/riscv/vector-iterators.md: New iterators.
	* config/riscv/vector.md
	(@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Remove.
	(@pred_indexed_<order>load<mode>_same_eew): New pattern.
	(@pred_indexed_<order>load<mode>_x2_greater_eew): Ditto.
	(@pred_indexed_<order>load<mode>_x4_greater_eew): Ditto.
	(@pred_indexed_<order>load<mode>_x8_greater_eew): Ditto.
	(@pred_indexed_<order>load<mode>_x2_smaller_eew): Ditto.
	(@pred_indexed_<order>load<mode>_x4_smaller_eew): Ditto.
	(@pred_indexed_<order>load<mode>_x8_smaller_eew): Ditto.
	(@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Remove.
	(@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
	(@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
	(@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
	(@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/merge_constraint-1.c: New test.