Skip to content
Snippets Groups Projects
Commit adbac207 authored by Li Xu's avatar Li Xu Committed by Pan Li
Browse files

RISC-V: Fix vector tuple intrinsic

Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex, vint32mf2x3_t v_tuple, size_t vl) {
  return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}

Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at config/riscv/riscv-vsetvl.cc:1679
   19 | }
      | ^
0x1439ec2 riscv_vector::vl_vtype_info::vl_vtype_info(riscv_vector::avl_info, unsigned char, riscv_vector::vlmul_type, unsigned char, bool, bool)
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1679
0x143f788 get_vl_vtype_info
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:807
0x143f788 riscv_vector::vector_insn_info::parse_insn(rtl_ssa::insn_info*)
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1843
0x1440371 riscv_vector::vector_infos_manager::vector_infos_manager()
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:2350
0x14407ee pass_vsetvl::init()
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4581
0x14471cf pass_vsetvl::execute(function*)
        ../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change
	scalar type to float16, eliminate warning.
	(vfloat16mf4x3_t): Ditto.
	(vfloat16mf4x4_t): Ditto.
	(vfloat16mf4x5_t): Ditto.
	(vfloat16mf4x6_t): Ditto.
	(vfloat16mf4x7_t): Ditto.
	(vfloat16mf4x8_t): Ditto.
	(vfloat16mf2x2_t): Ditto.
	(vfloat16mf2x3_t): Ditto.
	(vfloat16mf2x4_t): Ditto.
	(vfloat16mf2x5_t): Ditto.
	(vfloat16mf2x6_t): Ditto.
	(vfloat16mf2x7_t): Ditto.
	(vfloat16mf2x8_t): Ditto.
	(vfloat16m1x2_t): Ditto.
	(vfloat16m1x3_t): Ditto.
	(vfloat16m1x4_t): Ditto.
	(vfloat16m1x5_t): Ditto.
	(vfloat16m1x6_t): Ditto.
	(vfloat16m1x7_t): Ditto.
	(vfloat16m1x8_t): Ditto.
	(vfloat16m2x2_t): Ditto.
	(vfloat16m2x3_t): Ditto.
	(vfloat16m2x4_t): Ditto.
	(vfloat16m4x2_t): Ditto.
	* config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T.
	* config/riscv/vector.md: add tuple mode in attr sew.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/tuple-intrinsic.c: New test.
parent ade30fad
No related branches found
No related tags found
No related merge requests found
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment