i386: Generate strict_low_part QImode insn with high input register

Following testcase:

struct S1
{
  unsigned char val;
  unsigned char pad1;
  unsigned short pad2;
};

struct S2
{
  unsigned char pad1;
  unsigned char val;
  unsigned short pad2;
};

struct S1 test_and (struct S1 a, struct S2 b)
{
  a.val &= b.val;

  return a;
}

compiles with -O2 to:

	movl    %esi, %edx
	movl    %edi, %eax
	movzbl  %dh, %esi
	andb    %sil, %al

ANDB could use high register %dh instead of %sil:

	movl    %edi, %eax
	movl    %esi, %edx
	andb    %dh, %al

Patch introduces strict_low_part QImode insn patterns with one of
its input arguments extracted from high register.

	PR target/78904

gcc/ChangeLog:

	* config/i386/i386.md (*addqi_ext<mode>_1_slp):
	New define_insn_and_split pattern.
	(*subqi_ext<mode>_1_slp): Ditto.
	(*<any_logic:code>qi_ext<mode>_1_slp): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr78904-7.c: New test.
	* gcc.target/i386/pr78904-7a.c: New test.
	* gcc.target/i386/pr78904-7b.c: New test.