[14 regression] Fix insn types in risc-v port

So one of the broad goals we've had over the last few months has been to ensure
that every insn has a scheduling type and that every insn is associated with an
insn reservation in the scheduler.

This avoids some amazingly bad behavior in the scheduler.  I won't go through
the gory details.

I was recently analyzing a code quality regression with dhrystone (ugh!) and
one of the issues was poor scheduling which lengthened the lifetime of a pseudo
and ultimately resulted in needing an additional callee saved register
save/restore.

This was ultimately tracked down incorrect types on a few patterns.  So I did
an audit of all the patterns that had types added/changed as part of this
effort and found a variety of problems, primarily in the various move patterns
and extension patterns.  This is a regression relative to gcc-13.

Naturally the change in types affects scheduling, which in turn changes the
precise code we generate and causes some testsuite fallout.

I considered updating the regexps since the change in the resulting output is
pretty consistent.  But of course the test would still be sensitive to things
like load latency.  So instead I just turned off the 2nd phase scheduler in the
affected tests.

Bootstrapped and regression tested on rv64gc-linux-gnu.
gcc
	* config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
	type attribute.
	(extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
	(movdi_32bit, movdi_64bit, movsi_internal): Likewise.
	(movhi_internal, movqi_internal): Likewise.
	(movsf_softfloat, movsf_hardfloat): Likewise.
	(movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
	(movdf_softfloat): Likewise.

gcc/testsuite
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off
	second phase scheduler.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.