RISC-V: Quick and simple fixes to testcases that break due to reordering

The following test cases are easily fixed with small updates to the expected
assembly order. Additionally make calling-convention testcases more robust

	PR target/113249

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c:
	Rearrange and adjust asm-checker times
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c:
	Rearrange assembly
	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto
	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>