RISC-V: Dynamic adjust size of VLA vector according to TARGET_MIN_VLEN

This patch is to dynamic adjust size of VLA vectors according to TARGET_MIN_VLEN (-march=*zvl*b).

Currently, VNx16QImode is always [16,16] when TARGET_MINV_LEN >= 128.

We are going to add a bunch of VLS modes (V16QI,V32QI,....etc), these modes should always be considered
as having smaller size than VLA vectors.

For example, the V32QImode is LMUL = 1 VLS mode when TARGET_MIN_VLEN = 256
             and V16QImode is LMUL = 1 VLS mode when TARGET_MINV_LEN = 128.

Since a LMUL = 1 VLA mode VNx16QI is always [16,16] before this patch,
when TARGET_MIN_VLEN = 128, VNx16QImode ([16,16]) > V16QImode.
when TARGET_MIN_VLEN = 256, VNx16QImode ([16,16]) possible < V32QImode.

Then such inconsistency (TARGET_MIN_VLEN = 128, regno_reg_rtx[97] is VLA modes wheras it is VLS modes when TARGET_MIN_VLEN = 256).

This patch now adjust VLA vector size accurately according to TARGET_MIN_VLEN which make things more reasonable:

VNx16QI = [16,16] if TARGET_MIN_VLEN = 128.
VNx16QI = [32,32] if TARGET_MIN_VLEN = 256.
VNx16QI = [64,64] if TARGET_MIN_VLEN = 512.
VNx16QI = [128,128] if TARGET_MIN_VLEN = 1024.
VNx16QI = [256,256] if TARGET_MIN_VLEN = 2048.
VNx16QI = [512,512] if TARGET_MIN_VLEN = 4096.

gcc/ChangeLog:

	* config/riscv/riscv-selftests.cc (run_poly_int_selftests): Add more selftests.
	* config/riscv/riscv.cc (riscv_legitimize_poly_move): Dynamic adjust size of VLA vectors.
	(riscv_convert_vector_bits): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: New test.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: New test.