RISC-V: const: hide mvconst splitter from IRA

Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.

Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no code at all).

See PR/109279 (large constant), PR/110748 (const -0.0) ...

Granted the IRA logic is subsided with -fsched-pressure which is now
enabled for RISC-V backend, the gate makes this future-proof in
addition to helping with -O1 etc.

This fixes 1 addition test

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ | gfortran |

   rv32imac/  ilp32/ medlow |  416 /   103 |   13 /     6 |   67 /    12 |
 rv32imafdc/ ilp32d/ medlow |  416 /   103 |   13 /     6 |   24 /     4 |
   rv64imac/   lp64/ medlow |  417 /   104 |    9 /     3 |   67 /    12 |
 rv64imafdc/  lp64d/ medlow |  416 /   103 |    5 /     2 |    6 /     1 |

Also similar to v1, this doesn't move RISC-V SPEC scores at all.

gcc/ChangeLog:
	* config/riscv/riscv.md (mvconst_internal): Add !ira_in_progress.

Suggested-by: Jeff Law <jeffreyalaw@gmail.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>