[PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector

Since the THeadVector vsetvli does not support vl as an immediate, we
need to convert 0 to zero when outputting asm.

	PR target/116592

gcc/ChangeLog:

	* config/riscv/thead.cc (th_asm_output_opcode): Change '0' to
	"zero"

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test.