RISC-V: Disallow RVV mode address for any load/store[PR112535]

This patch is quite obvious patch which disallow for load/store address register
with RVV mode.

	PR target/112535

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV modes base address.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112535.c: New test.