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RISC-V: Allow CONST_VECTOR for VLS modes
This patch enables COSNT_VECTOR for VLS modes. void foo1 (int * __restrict a) { for (int i = 0; i < 16; i++) a[i] = 8; } void foo2 (int * __restrict a) { for (int i = 0; i < 16; i++) a[i] = i; } Compile option: -O3 --param=riscv-autovec-preference=scalable Before this patch: foo1: lui a5,%hi(.LC0) addi a5,a5,%lo(.LC0) vsetivli zero,4,e32,m1,ta,ma addi a4,a0,16 vle32.v v1,0(a5) vse32.v v1,0(a0) vse32.v v1,0(a4) addi a4,a0,32 vse32.v v1,0(a4) addi a0,a0,48 vse32.v v1,0(a0) ret foo2: lui a5,%hi(.LC1) addi a5,a5,%lo(.LC1) vsetivli zero,4,e32,m1,ta,ma vle32.v v1,0(a5) lui a5,%hi(.LC2) addi a5,a5,%lo(.LC2) vse32.v v1,0(a0) vle32.v v1,0(a5) lui a5,%hi(.LC3) addi a4,a0,16 addi a5,a5,%lo(.LC3) vse32.v v1,0(a4) vle32.v v1,0(a5) addi a4,a0,32 lui a5,%hi(.LC4) vse32.v v1,0(a4) addi a0,a0,48 addi a5,a5,%lo(.LC4) vle32.v v1,0(a5) vse32.v v1,0(a0) ret After this patch: foo1: vsetivli zero,16,e32,mf2,ta,ma vmv.v.i v1,8 vse32.v v1,0(a0) ret .size foo1, .-foo1 .align 1 .globl foo2 .type foo2, @function foo2: vsetivli zero,16,e32,mf2,ta,ma vid.v v1 vse32.v v1,0(a0) ret gcc/ChangeLog: * config/riscv/autovec.md: Add VLS CONST_VECTOR. * config/riscv/riscv.cc (riscv_const_insns): Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS CONST_VECTOR tests. * gcc.target/riscv/rvv/autovec/vls/const-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/const-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/const-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/const-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/const-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/series-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/series-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/series-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/series-4.c: New test.
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- gcc/config/riscv/autovec.md 1 addition, 1 deletiongcc/config/riscv/autovec.md
- gcc/config/riscv/riscv.cc 1 addition, 1 deletiongcc/config/riscv/riscv.cc
- gcc/config/riscv/vector.md 4 additions, 4 deletionsgcc/config/riscv/vector.md
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h 14 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c 40 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
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