RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

In previous, we have some specially handling for both the .SAT_ADD and
.SAT_SUB for unsigned int.  There are similar to take care of SImode
in RV64 for zero extend.  Thus refactor these two helper function
into one for possible code duplication.

The below test suite are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Merge
	the zero_extend handing from func riscv_gen_unsigned_xmode_reg.
	(riscv_gen_unsigned_xmode_reg): Remove.
	(riscv_expand_ussub): Leverage riscv_gen_zero_extend_rtx
	instead of riscv_gen_unsigned_xmode_reg.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_sub-11.c: Adjust asm check.
	* gcc.target/riscv/sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/sat_u_sub-43.c: Ditto.
	* gcc.target/riscv/sat_u_sub-47.c: Ditto.
	* gcc.target/riscv/sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-11.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-11_1.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-11_2.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-15.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-15_1.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-15_2.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-3.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-3_1.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-3_2.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-7.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-7_1.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-7_2.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>