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RISC-V: Fix constraint bug for binary operation
Current constraint configuration will generate: vadd.vv v0,v24,v25,v0.t vsll.vx v0,v24,a5,v0.t They are incorrect according to RVV ISA. This patch fix this obvious issue. gcc/ChangeLog: * config/riscv/vector-iterators.md (sll.vi): Fix constraint bug. (sll.vv): Ditto. (%3,%4): Ditto. (%3,%v4): Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c:
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- gcc/config/riscv/vector-iterators.md 43 additions, 43 deletionsgcc/config/riscv/vector-iterators.md
- gcc/config/riscv/vector.md 23 additions, 18 deletionsgcc/config/riscv/vector.md
- gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c 4 additions, 4 deletions...stsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
- gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c 5 additions, 4 deletions...stsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
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