The URL where to report bugs is hard coded in two places; abstract that
into one variable, defined up front.

maintainer-scripts/ChangeLog:

	* update_web_docs_git (BUGURL): Introduce and use throughout.

When flatten_await_stmt processes the backing array for an initializer_list,
we call cp_build_modify_expr to initialize the promoted variable from the
TARGET_EXPR; that needs to be accepted.

	PR c++/103871
	PR c++/98056

gcc/cp/ChangeLog:

	* typeck.cc (cp_build_modify_expr): Allow array initialization of
	DECL_ARTIFICIAL variable.

gcc/testsuite/ChangeLog:

	* g++.dg/coroutines/co-await-initlist1.C: New test.

As noted in PR analyzer/109097, if an internal compiler error occurs
when -fdiagnostics-format=sarif-file is specified, we currently fail
to write out a .sarif file, and the output to stderr doesn't contain
"internal compiler error" or "Internal compiler error"; just the
backtrace if we're lucky, and the "Please submit a full bug report"
messages.

This is a nuisance e.g. for my integration testing of -fanalyzer, where
I'm gathering the results of builds via the .sarif output: if it crashes
on a particular source file, then no output is generated, and it's
effectively silent about the crash.

This patch fixes things by adding a callback to diagnostic_context so
that the SARIF output code can make one final attempt to write its
output if an ICE occurs.  It also special-cases the output, so that an
ICE is treated as an "error"-level "notification" relating to the
operation of the tool (SARIF v2.1.0 section 3.58), rather than a
"result" about the code being analyzed by the tool.

The patch adds test coverage for this via a plugin that can inject:
* calls to internal_compiler_error, and
* writes through a NULL pointer
and verifying that a  .sarif file is written out capturing the crash
(and also that an ICE occurs via dg-ice, which seems to treat the ICE as
an XFAIL, which is reasonable).

I've added support for this to my integration-testing scripts: testing
shows that with this patch we capture analyzer crashes in .sarif files
(specifically, the analyzer crash on qemu: PR analyzer/109094), and I've
updated my scripts to work with and report such output.

I manually verified that the resulting .sarif files validate against the
schema.

gcc/ChangeLog:
	PR analyzer/109097
	* diagnostic-format-sarif.cc (class sarif_invocation): New.
	(class sarif_ice_notification): New.
	(sarif_builder::m_invocation_obj): New field.
	(sarif_invocation::add_notification_for_ice): New.
	(sarif_invocation::prepare_to_flush): New.
	(sarif_ice_notification::sarif_ice_notification): New.
	(sarif_builder::sarif_builder): Add m_invocation_obj.
	(sarif_builder::end_diagnostic): Special-case DK_ICE and
	DK_ICE_NOBT.
	(sarif_builder::flush_to_file): Call prepare_to_flush on
	m_invocation_obj.  Pass the latter to make_top_level_object.
	(sarif_builder::make_result_object): Move creation of "locations"
	array to...
	(sarif_builder::make_locations_arr): ...this new function.
	(sarif_builder::make_top_level_object): Add "invocation_obj" param
	and pass it to make_run_object.
	(sarif_builder::make_run_object): Add "invocation_obj" param and
	use it.
	(sarif_ice_handler): New callback.
	(diagnostic_output_format_init_sarif): Wire up sarif_ice_handler.
	* diagnostic.cc (diagnostic_initialize): Initialize new field
	"ice_handler_cb".
	(diagnostic_action_after_output): If it is set, make one attempt
	to call ice_handler_cb.
	* diagnostic.h (diagnostic_context::ice_handler_cb): New field.

gcc/testsuite/ChangeLog:
	PR analyzer/109097
	* c-c++-common/diagnostic-format-sarif-file-1.c: Verify that we
	have an invocation object marked as succeeding, with no
	notifications.
	* gcc.dg/plugin/crash-test-ice-sarif.c: New test.
	* gcc.dg/plugin/crash-test-ice-stderr.c: New test.
	* gcc.dg/plugin/crash-test-write-though-null-sarif.c: New test.
	* gcc.dg/plugin/crash-test-write-though-null-stderr.c: New test.
	* gcc.dg/plugin/crash_test_plugin.c: New plugin.
	* gcc.dg/plugin/plugin.exp (plugin_test_list): Add the new plugin
	and test cases.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

This patch fixes more bool int parameter mismatches
found in dtoa and ldtoa.

gcc/m2/ChangeLog:

	PR modula2/109125
	* gm2-libs-ch/dtoa.cc (dtoa_strtod): Replace int with bool.
	* gm2-libs-ch/ldtoa.cc (ldtoa_strtold): Replace int with bool.

libgm2/ChangeLog:

	PR modula2/109125
	* libm2pim/dtoa.cc (TRUE): Remove.
	(FALSE): Remove.  Replace int with bool.
	* libm2pim/ldtoa.cc (TRUE): Remove.
	(FALSE): Remove.  Replace int with bool.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

8-byte modes should be processed only for TARGET_MMX_WITH_SSE. Handle
V2SFmode and fix V2HImode handling. The resulting BLEND instructions
are always faster than MOVSS/MOVSD, so prioritize them w.r.t MOVSS/MOVSD
for TARGET_SSE4_1.

gcc/ChangeLog:

	* config/i386/i386-expand.cc (expand_vec_perm_blend):
	Handle 8-byte modes only with TARGET_MMX_WITH_SSE. Handle V2SFmode
	and fix V2HImode handling.
	(expand_vec_perm_1): Try to emit BLEND instruction
	before MOVSS/MOVSD.
	* config/i386/mmx.md (*mmx_blendps): New insn pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/merge-1.c (dg-options): Use -mno-sse4.
	* gcc.target/i386/sse2-mmx-21.c (dg-options): Ditto.
	* gcc.target/i386/sse-movss-4.c (dg-options):
	Use -mno-sse4.  Simplify scan-assembler-not strings.
	* gcc.target/i386/sse2-movsd-3.c (dg-options): Ditto.
	* gcc.target/i386/sse2-mmx-movss-1.c: New test.

gcc/fortran/ChangeLog:

	PR fortran/58331
	* interface.cc (compare_parameter): Adjust check of array dummy
	arguments to handle the case of CLASS variables.

gcc/testsuite/ChangeLog:

	PR fortran/58331
	* gfortran.dg/class_dummy_10.f90: New test.

Co-authored-by: Tobias Burnus <tobias@codesourcery.com>

We crash here since r10-3661, the store_init_value hunk in particular.
Before, we called cp_fully_fold_init, so e.g.

  {.str=VIEW_CONVERT_EXPR<char[8]>("")}

was folded into

  {.str=""}

but now we don't fold and keep the VCE around, and it causes trouble in
cxx_eval_store_expression: in the !refs->is_empty () loop we descend on
.str's initializer but since it's wrapped in a VCE, we skip the STRING_CST
check and then crash on the CONSTRUCTOR_NO_CLEARING.

	PR c++/107280

gcc/cp/ChangeLog:

	* constexpr.cc (cxx_eval_store_expression): Strip location wrappers.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp1z/constexpr-lambda28.C: New test.

gcc/
	* omp-low.cc (omp_runtime_api_call): Add omp_in_explicit_task.

We are diagnosing

  operator delete (this_3(D));
  A::f (this_3(D));
  *this_3(D) ={v} CLOBBER;

where the CLOBBER appears at the end of the DTOR for C++11 and later.
The following avoids this by simply never diagnosing clobbers as
use-after-free.

	* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
	Do not diagnose clobbers.

	* g++.dg/warn/Wuse-after-free3.C: Remove expected duplicate
	diagnostic.

This function needs to handle this case like convert_template_argument.

	PR c++/58538

gcc/cp/ChangeLog:

	* semantics.cc (check_template_template_default_arg): Check
	maybe_get_template_decl_from_type_decl.

gcc/testsuite/ChangeLog:

	* g++.dg/template/ttp7.C: Remove expected error.

I kept trying to improve our choice of how many levels of outer_args to add,
when really the problem was that outer_args are for PARM and for this
reverse deduction we should be adding the outer arguments for ARG.

I spent quite a while trying to get DECL_CONTEXT set consistently on
template template parameters that have gone through
reduce_template_parm_level before I realized I could just use
current_scope().

	PR c++/108179
	PR c++/104107
	PR c++/95036

gcc/cp/ChangeLog:

	* pt.cc (coerce_template_template_parms): Use args from
	DECL_CONTEXT (arg_tmpl) instead of outer_args.

gcc/testsuite/ChangeLog:

	* g++.dg/template/ttp35.C: New test.

This should have no semantic effect, but is a prerequisite for the PR108179
fix to follow.

	PR c++/108179

gcc/cp/ChangeLog:

	* pt.cc	(coerce_template_template_parms): Take the arg and parm
	templates directly.
	(coerce_template_template_parm): Adjust.
	(template_template_parm_bindings_ok_p): Adjust.
	(convert_template_argument): Adjust.

The following make sure to strip MEMs when looking for unused
decls on the LHS of .DEFERRED_INIT.

	PR tree-optimization/109139
	* tree-ssa-live.cc (remove_unused_locals): Look at the
	base address for unused decls on the LHS of .DEFERRED_INIT.

	* gcc.dg/torture/pr109139.c: New testcase.

expand_simple_binop() is allowed to allocate a new pseudo-register and
return it, instead of forcing the result into the provided
pseudo-register.  This can cause a problem when we expand the unrolled
loop for __builtin_strcmp: the compiler always generates code for all n
iterations of the loop, so "result" will be an alias of the
pseudo-register allocated and used in the last iteration; but at runtime
the loop can break early, causing this pseudo-register uninitialized.

Emit a move instruction in the iteration to force the difference into
one register which has been allocated before the loop, to avoid this
issue.

gcc/ChangeLog:

	PR other/109086
	* builtins.cc (inline_string_cmp): Force the character
	difference into "result" pseudo-register, instead of reassign
	the pseudo-register.

The XTheadMemPair ISA extension allows to pair two loads or stores:
* th.ldd (2x LD)
* th.lwd (2x LW)
* th.lwud (2x LWU)
* th.sdd (2x SD)
* th.swd (2x SW)

The displacement of these instructions is quite limited:
* Displacement := imm2 << shamt
* imm2 is a 2-bit unsigned value {0..3}
* shamt is 4 for th.ldd/th.sdd and 3 otherwise
But even with this small displacement we can identify many candidates.

The merge of the two loads/stores is realized in form of peephole2
passes that support instruction reordering.
The CFA expansion (save/restore registers on/from stack) is not
processed by the peephole2 pass and, therefore, needs special-treatment.
Many ideas of this patch are inspired by similar/equal approaches
in other backends.

gcc/ChangeLog:

	* config.gcc: Add thead.o to RISC-V extra_objs.
	* config/riscv/peephole.md: Add mempair peephole passes.
	* config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New
	prototype.
	(th_mempair_operands_p): Likewise.
	(th_mempair_order_operands): Likewise.
	(th_mempair_prepare_save_restore_operands): Likewise.
	(th_mempair_save_restore_regs): Likewise.
	(th_mempair_output_move): Likewise.
	* config/riscv/riscv.cc (riscv_save_reg): Move code.
	(riscv_restore_reg): Move code.
	(riscv_for_each_saved_reg): Add code to emit mempair insns.
	* config/riscv/t-riscv: Add thead.cc.
	* config/riscv/thead.md (*th_mempair_load_<GPR:mode>2):
	New insn.
	(*th_mempair_store_<GPR:mode>2): Likewise.
	(*th_mempair_load_extendsidi2): Likewise.
	(*th_mempair_load_zero_extendsidi2): Likewise.
	* config/riscv/thead.cc: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadmempair-1.c: New test.
	* gcc.target/riscv/xtheadmempair-2.c: New test.
	* gcc.target/riscv/xtheadmempair-3.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

The XTheadFmv ISA extension provides instructions to move
data between 32-bit GP registers and 64-bit FP registers.

Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/ChangeLog:

	* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
	New constraint "th_f_fmv".
	(TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint
	"th_r_fmv".
	* config/riscv/riscv.cc (riscv_split_doubleword_move):
	Add split code for XTheadFmv.
	(riscv_secondary_memory_needed): XTheadFmv does not need
	secondary memory.
	* config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and
	UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to
	movdf_hardfloat_rv32.
	* config/riscv/thead.md (th_fmv_hw_w_x): New INSN.
	(th_fmv_x_w): New INSN.
	(th_fmv_x_hw): New INSN.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmv-fmv.c: New test.

The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh

To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4

Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/ChangeLog:

	* config/riscv/riscv.md (maddhisi4): New expand.
	(msubhisi4): New expand.
	* config/riscv/thead.md (*th_mula<mode>): New pattern.
	(*th_mulawsi): New pattern.
	(*th_mulawsi2): New pattern.
	(*th_maddhisi4): New pattern.
	(*th_sextw_maddhisi4): New pattern.
	(*th_muls<mode>): New pattern.
	(*th_mulswsi): New pattern.
	(*th_mulswsi2): New pattern.
	(*th_msubhisi4): New pattern.
	(*th_sextw_msubhisi4): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadmac-mula-muls.c: New test.

This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding mov<mode>cc accordingly and adjust the cost
model.

gcc/ChangeLog:

	* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
	* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
	Add prototype.
	* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
	XTheadCondMov.
	(riscv_expand_conditional_move): New function.
	(riscv_expand_conditional_move_onesided): New function.
	* config/riscv/riscv.md: Add support for XTheadCondMov.
	* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
	support for XTheadCondMov.
	(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
	* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
	* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard extensions (e.g. by using INSN expand pattern that
will re-emit RTL that matches the patterns of either Bitmanip or
XThead INSNs).

gcc/ChangeLog:

	* config/riscv/bitmanip.md (clzdi2): New expand.
	(clzsi2): New expand.
	(ctz<mode>2): New expand.
	(popcount<mode>2): New expand.
	(<bitmanip_optab>si2): Rename INSN.
	(*<bitmanip_optab>si2): Hide INSN name.
	(<bitmanip_optab>di2): Rename INSN.
	(*<bitmanip_optab>di2): Hide INSN name.
	(rotrsi3): Remove INSN.
	(rotr<mode>3): Add expand.
	(*rotrsi3): New INSN.
	(rotrdi3): Rename INSN.
	(*rotrdi3): Hide INSN name.
	(rotrsi3_sext): Rename INSN.
	(*rotrsi3_sext): Hide INSN name.
	(bswap<mode>2): Remove INSN.
	(bswapdi2): Add expand.
	(bswapsi2): Add expand.
	(*bswap<mode>2): Hide INSN name.
	* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign
	extraction.
	* config/riscv/riscv.md (extv<mode>): New expand.
	(extzv<mode>): New expand.
	* config/riscv/thead.md (*th_srri<mode>3): New INSN.
	(*th_ext<mode>): New INSN.
	(*th_extu<mode>): New INSN.
	(*th_clz<mode>2): New INSN.
	(*th_rev<mode>2): New INSN.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadbb-ext.c: New test.
	* gcc.target/riscv/xtheadbb-extu-2.c: New test.
	* gcc.target/riscv/xtheadbb-extu.c: New test.
	* gcc.target/riscv/xtheadbb-ff1.c: New test.
	* gcc.target/riscv/xtheadbb-rev.c: New test.
	* gcc.target/riscv/xtheadbb-srri.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
	* config/riscv/thead.md (*th_tst<mode>3): New INSN.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadbs-tst.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.

gcc/ChangeLog:

	* config/riscv/riscv.md: Include thead.md
	* config/riscv/thead.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadba-addsl.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-thead-c906.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This patch add basic support for the following XThead* ISA extensions:

* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync

The extensions are just recognized by the compiler and feature test
macros are generated (which this patch also brings tests for).

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add xthead* extensions.
	* config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
	(MASK_XTHEADBB): New.
	(MASK_XTHEADBS): New.
	(MASK_XTHEADCMO): New.
	(MASK_XTHEADCONDMOV): New.
	(MASK_XTHEADFMEMIDX): New.
	(MASK_XTHEADFMV): New.
	(MASK_XTHEADINT): New.
	(MASK_XTHEADMAC): New.
	(MASK_XTHEADMEMIDX): New.
	(MASK_XTHEADMEMPAIR): New.
	(MASK_XTHEADSYNC): New.
	(TARGET_XTHEADBA): New.
	(TARGET_XTHEADBB): New.
	(TARGET_XTHEADBS): New.
	(TARGET_XTHEADCMO): New.
	(TARGET_XTHEADCONDMOV): New.
	(TARGET_XTHEADFMEMIDX): New.
	(TARGET_XTHEADFMV): New.
	(TARGET_XTHEADINT): New.
	(TARGET_XTHEADMAC): New.
	(TARGET_XTHEADMEMIDX): New.
	(TARGET_XTHEADMEMPAIR): new.
	(TARGET_XTHEADSYNC): New.
	* config/riscv/riscv.opt: Add riscv_xthead_subext.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadba.c: New test.
	* gcc.target/riscv/xtheadbb.c: New test.
	* gcc.target/riscv/xtheadbs.c: New test.
	* gcc.target/riscv/xtheadcmo.c: New test.
	* gcc.target/riscv/xtheadcondmov.c: New test.
	* gcc.target/riscv/xtheadfmemidx.c: New test.
	* gcc.target/riscv/xtheadfmv.c: New test.
	* gcc.target/riscv/xtheadint.c: New test.
	* gcc.target/riscv/xtheadmac.c: New test.
	* gcc.target/riscv/xtheadmemidx.c: New test.
	* gcc.target/riscv/xtheadmempair.c: New test.
	* gcc.target/riscv/xtheadsync.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/ChangeLog:

	PR target/109117
	* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
	__builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
	__builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL.

gcc/testsuite/ChangeLog:

	PR target/109117
	* gcc.target/i386/pr109117-1.c: New test.

gcc/testsuite/ChangeLog:

	* gcc.dg/pic-2.c: Fix expected __PIC__ value.
	* gcc.dg/pic-3.c: Ditto.
	* gcc.dg/pic-4.c: Ditto.

Signed-off-by: Jonathan Yong <10walls@gmail.com>

An out-of-line definition of a member of a constrained class template
needs to repeat the template's constraints, but it turns out we don't
verify anywhere that the two sets of constraints match.  This patch
adds such a check to push_template_decl, nearby a similar consistency
check for the template parameter list lengths.

	PR c++/96830

gcc/cp/ChangeLog:

	* pt.cc (push_inline_template_parms_recursive): Set
	TEMPLATE_PARMS_CONSTRAINTS.
	(push_template_decl): For an out-of-line declaration, verify
	constraints for each enclosing template scope match those of the
	original template declaratation.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/concepts-class5.C: New test.
	* g++.dg/cpp2a/concepts-class5a.C: New test.

When instantiating a constrained template friend naming an already
declared class template, tsubst_friend_class erroneously passes to
redeclare_class_template the existing template's constraints instead of
those of the friend declaration, which causes the constraint comparison
check therein to trivially succeed and we fail to diagnose legitimate
constraint mismatches.

	PR c++/96830

gcc/cp/ChangeLog:

	* pt.cc (redeclare_class_template): Add missing "of" in
	constraint mismatch diagnostic.
	(tsubst_friend_class): For an already declared class template,
	substitute and pass the friend declaration's constraints to
	redeclare_class_template instead of passing the existing
	template's constraints.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/concepts-friend14.C: New test.

	PR libstdc++/109111

libstdc++-v3/ChangeLog:

	* include/std/ranges (repeat_view): Remove redundant parentheses
	in requires-clause.
	(repeat_view::_Iterator): Correct the requires-clause.

Generally we expect TPARMS_PRIMARY_TEMPLATE to be set, but sometimes it
isn't for partial instantiations.  This ought to be improved, but it's
trivial to work around it in this case.

	PR c++/108468

gcc/cp/ChangeLog:

	* pt.cc (unify_pack_expansion): Check that TPARMS_PRIMARY_TEMPLATE
	is non-null.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp1y/var-templ78.C: New test.

libstdc++-v3/ChangeLog:

	* include/bits/stl_iterator.h (move_iterator::_S_iter_concept):
	Define.
	(__cpp_lib_move_iterator_concept): Define for C++20.
	(move_iterator::iterator_concept): Strengthen as per P2520R0.
	* include/std/version (__cpp_lib_move_iterator_concept): Define
	for C++20.
	* testsuite/24_iterators/move_iterator/p2520r0.cc: New test.

libstdc++-v3/ChangeLog:

	* include/bits/ranges_util.h (view_interface::empty): Add
	preferred overloads that use ranges::size when the range is
	sized as per LWG 3715.
	* testsuite/std/ranges/adaptors/lwg3715.cc: New test.

13 regression failures seen on sparc SIGBUS in m2pim_ldtoa_ldtoa.
This patch fixes int bool parameter mismatches between the
definition modules and their C/C++ implementations.

gcc/m2/ChangeLog:

	PR modula2/109125
	* gm2-libs-ch/cgetopt.c (cgetopt_SetOption): Replace int
	for bool.
	* gm2-libs-ch/termios.c (doSetUnset): Replace int for bool.
	* gm2-libs/Builtins.mod (isfinitef): Correct typo in return
	statement.

libgm2/ChangeLog:

	PR modula2/109125
	* libm2iso/ErrnoCategory.cc (FALSE): Remove.
	(TRUE): Remove.
	* libm2iso/wrapsock.c (TRUE): Remove.
	(FALSE): Remove.
	* libm2iso/wraptime.cc (TRUE): Remove.
	(FALSE): Remove.
	* libm2pim/cgetopt.cc: Replace int for bool for every BOOLEAN
	parameter in the definition module.
	* libm2pim/dtoa.cc: Ditto.
	* libm2pim/ldtoa.cc: Ditto.
	* libm2pim/termios.cc: Ditto.
	(doSetUnset): Replace int for bool.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

I removed this folding in GCC 12 because it was interfering with an
experiment of richi's, but that never went in and the change causes
regressions, so let's put it back.

This reverts commit r12-5638-ga3e75c1491cd2d.

	PR c++/107310

gcc/cp/ChangeLog:

	* cp-gimplify.cc (genericize_if_stmt): Restore folding
	of constant conditions.

gcc/testsuite/ChangeLog:

	* c-c++-common/Wimplicit-fallthrough-39.c: Adjust warning.
	* g++.dg/warn/Wreturn-6.C: New test.

In my PR107627 change I've missed one important case, which causes
miscompilation of f4 and f6 in the following tests.

Combine matches there *concatsidi3_3 define_insn_and_split (as with all
other f* functions in those tests), and RA ends up with:
(insn 11 10 17 2 (set (reg:DI 0 ax [89])
        (ior:DI (ashift:DI (zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI 0 ax [94])
                                (const_int 4 [0x4]))
                            (symbol_ref:SI ("arr") [flags 0x2]  <var_decl 0x7f4e7fe4ccf0 arr>)) [1 arr[ax_6(D)]+0 S4 A32]))
                (const_int 32 [0x20]))
            (zero_extend:DI (reg:SI 1 dx [95])))) "pr109109-6.c":24:49 681 {*concatsidi3_3}
     (nil))
split_double_concat turned that into:
        movl    arr(,%eax,4), %edx
        movl    %edx, %eax
which is incorrect, because the first instruction overrides the input
%edx value that should be put into output %eax; the two insns can't be
swapped because the MEM's address uses %eax.

The following patch fixes that case to emit
        movl    arr(,%eax,4), %eax
        xchgl   %edx, %eax
instead.

2023-03-14  Jakub Jelinek  <jakub@redhat.com>

	PR target/109109
	* config/i386/i386-expand.cc (split_double_concat): Fix splitting
	when lo is equal to dhi and hi is a MEM which uses dlo register.

	* gcc.target/i386/pr109109-1.c: New test.
	* gcc.target/i386/pr109109-2.c: New test.

Previously lambdas were connected to the module they were defined in.
Now they are emitted into every referencing compilation unit, and are
given one-only linkage.

	PR d/109108

gcc/d/ChangeLog:

	* decl.cc (function_defined_in_root_p): Remove.
	(get_symbol_decl): Set DECL_LAMBDA_FUNCTION_P on function literals.
	(start_function): Unconditionally unset DECL_EXTERNAL
	(set_linkage_for_decl): Give lambda functions one-only linkage.

gcc/testsuite/ChangeLog:

	* gdc.dg/torture/imports/pr109108.d: New test.
	* gdc.dg/torture/pr109108.d: New test.

Looking into the behavior of profile count updating in PR 107925, I
noticed that an option not considered possible was actually happening,
and - with the guesswork in place to distribute unexplained counts -
it simply can happen.  Currently it is handled by dropping the counts
to local estimated zero, whereas it is probably better to leave the
count as they are but drop the category to GUESSED_GLOBAL0 - which is
what profile_count::combine_with_ipa_count in a similar case (or so I
hope :-)

gcc/ChangeLog:

2023-02-20  Martin Jambor  <mjambor@suse.cz>

	PR ipa/107925
	* ipa-cp.cc (update_profiling_info): Drop counts of orig_node to
	global0 instead of zeroing when it does not have as many counts as
	it should.

The patch below fixes various issues in function
update_specialized_profile.  The main is removal of the assert which
is bogus in the case of recursive cloning.  The division of
unexplained counts is guesswork, which then leads to updates of counts
of recursive edges, which then can be redirected to the new clone and
their count subtracted from the count and there simply may not be
enough left in the count of the original node - especially when we
clone a lot because of using --param ipa-cp-eval-threshold=1.

The other issue was omission to drop the count of the original node to
ipa count.  And when calculating the remainder, we should use
lenient_count_portion_handling to account for partial train runs.
Finally, the patch adds dumping of the original count which I think
is useful.

gcc/ChangeLog:

2023-02-17  Martin Jambor  <mjambor@suse.cz>

	PR ipa/107925
	* ipa-cp.cc (update_specialized_profile): Drop orig_node_count to
	ipa count, remove assert, lenient_count_portion_handling, dump
	also orig_node_count.

Perform V2SI vector permutation in the same way as existing V2SF for
TARGET_MMX_WITH_SSE targets. The testcase:

typedef unsigned int v2si __attribute__((vector_size(8)));
v2si foo(v2si x, v2si y) { return (v2si){y[0], x[1]}; }

is currently compiled to (-O2):

foo:
	movdqa  %xmm0, %xmm2
	movdqa  %xmm1, %xmm0
	pshufd  $0xe5, %xmm2, %xmm2
	punpckldq %xmm2, %xmm0
	ret

and with the patched compiler:

foo:
	movss   %xmm1, %xmm0
	ret

The functionality is already tested in gcc.target/i386/vperm-v2si.c

gcc/ChangeLog:

	* config/i386/i386-expand.cc (expand_vec_perm_movs):
	Handle V2SImode for TARGET_MMX_WITH_SSE.
	* config/i386/mmx.md (*mmx_movss_<mode>): Rename from *mmx_movss
	using V2FI mode iterator to handle both V2SI and V2SF modes.