We now use a C++ compiler so that we need to process
CXXFLAGS as well as CFLAGS in the gcc-plugin config
fragment.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>

config/ChangeLog:

	* gcc-plugin.m4: Save and process CXXFLAGS.

gcc/ChangeLog:

	* configure: Regenerate.

libcc1/ChangeLog:

	* configure: Regenerate.

Add new target macros TARGET_SM75 and TARGET_SM80.  Add support for
__builtin_tanhf, HFmode exp2/tanh and also for HFmode min/max, controlled by
TARGET_SM75 and TARGET_SM80 respectively.

The following has been tested on nvptx-none, hosted on x86_64-pc-linux-gnu
with a "make" and "make -k check" with no new failures.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (ptx_isa): PTX_ISA_SM75 and PTX_ISA_SM80
	ISA levels.
	* config/nvptx/nvptx.opt: Add sm_75 and sm_80 to -misa.
	* config/nvptx/nvptx.h (TARGET_SM75, TARGET_SM80):
	New helper macros to conditionalize functionality on target ISA.
	* config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
	support for the new ISA levels.
	* config/nvptx/nvptx.c (nvptx_file_start): Add support for TARGET_SM75
	and TARGET_SM80.
	* config/nvptx/nvptx.md (define_c_enum "unspec"): New UNSPEC_TANH.
	(define_mode_iterator HSFM): New iterator for HFmode and SFmode.
	(exp2hf2): New define_insn controlled by TARGET_SM75.
	(tanh<mode>2): New define_insn controlled by TARGET_SM75.
	(sminhf3, smaxhf3): New define_isnns controlled by TARGET_SM80.

gcc/testsuite/ChangeLog:

	* gcc.target/nvptx/float16-2.c: New test case.
	* gcc.target/nvptx/tanh-1.c: New test case.

Add support for ptx isa version 7.0, required for the addition of -misa=sm_75
and -misa=sm_80.

Tested by setting the default ptx isa version to 7.0, and doing a build and
libgomp test run.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_7_0.
	* config/nvptx/nvptx.c (nvptx_file_start): Handle TARGET_PTX_7_0.
	* config/nvptx/nvptx.h (TARGET_PTX_7_0): New macro.
	* config/nvptx/nvptx.opt (ptx_version): Add 7.0.

In this PR we were wrongly classifying a pair of 8-byte vectors
as a 16-byte “short vector” (in the AAPCS64 sense).  As the
comment in the patch says, this stems from an old condition
in aarch64_short_vector_p that is too loose, but that would
be difficult to tighten now.

We can still do the right thing for the newly-added modes though,
since there are no backwards compatibility concerns there.

Co-authored-by: Tamar Christina <tamar.christina@arm.com>

gcc/
	PR target/103094
	* config/aarch64/aarch64.c (aarch64_short_vector_p): Return false
	for structure modes, rather than ignoring the type in that case.

gcc/testsuite/
	PR target/103094
	* gcc.target/aarch64/pr103094.c: New test.

	PR c++/103713

gcc/cp/ChangeLog:

	* tree.c (maybe_warn_parm_abi): Fix warning word splitting.

This and the report in PR103632 are caused by a bug in REE where it generates
incorrect code.

It's trying to eliminate the following zero extension

(insn 54 90 102 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))

by folding it in the definition of `v8`:

(insn 2 5 104 2 (set (reg/v:V4HI 40 v8)
        (reg:V4HI 32 v0 [156]))
     (nil))

which is fine, except that `v8` is also used by the extracts, e.g.:

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8)
                (parallel [
                        (const_int 3)
                    ]))))
     (nil))

REE replaces insn 2 by folding insn 54 and placing it at the definition site of
insn 2, so before insn 11.

Trying to eliminate extension:
(insn 54 90 102 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))
Tentatively merged extension with definition (copy needed):
(insn 2 5 104 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg:V4HI 32 v0)))
     (nil))

to produce

(insn 2 5 110 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg:V4HI 32 v0)))
     (nil))
(insn 110 2 104 2 (set (reg:V4SI 40 v8)
        (reg:V4SI 33 v1))
     (nil))

The new insn 2 using v0 directly is correct, but the insn 110 it creates is
wrong, `v8` should still be V4HI.

or it also needs to eliminate the zero extension from the extracts, so instead
of

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8)
                (parallel [
                        (const_int 3)
                    ]))))
     (nil))

it should be

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (vec_select:SI (reg/v:V4SI 40 v8)
                (parallel [
                        (const_int 3)
                    ])))
     (nil))

without doing so the indices have been remapped in the extension and so we
extract the wrong elements

At any other optimization level but -Os ree seems to abort so this doesn't
trigger:

Trying to eliminate extension:
(insn 54 90 101 2 (set (reg:V4SI 32 v0)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))
Elimination opportunities = 2 realized = 0

purely due to the ordering of instructions. REE doesn't check uses of `v8`
because it assumes that with a zero extended value, you still have access to the
lower bits by using the the bottom part of the register.

This is true for scalar but not for vector.  This would have been fine as well
if REE had eliminated the zero_extend on insn 11 and the rest but it doesn't do
so since REE can only handle cases where the SRC value are REG_P.

It does try to do this in add_removable_extension:

 1160      /* For vector mode extensions, ensure that all uses of the
 1161         XEXP (src, 0) register are in insn or debug insns, as unlike
 1162         integral extensions lowpart subreg of the sign/zero extended
 1163         register are not equal to the original register, so we have
 1164         to change all uses or none and the current code isn't able
 1165         to change them all at once in one transaction.  */

However this code doesn't trigger for the example because REE doesn't check the
uses if the defining instruction doesn't feed into another extension..

Which is bogus. For vectors it should always check all usages.

r12-2288-g8695bf78dad1a42636775843ca832a2f4dba4da3 simply exposed this as it now
lowers VEC_SELECT 0 into the RTL canonical form subreg 0 which causes REE to run
more often.

gcc/ChangeLog:

	PR rtl-optimization/103350
	* ree.c (add_removable_extension): Don't stop at first definition but
	inspect all.

gcc/testsuite/ChangeLog:

	PR rtl-optimization/103350
	* gcc.target/aarch64/pr103350-1.c: New test.
	* gcc.target/aarch64/pr103350-2.c: New test.

This test fails:
+FAIL: g++.dg/cpp23/auto-fncast11.C  -std=c++2b  (test for errors, line 19)
+FAIL: g++.dg/cpp23/auto-fncast11.C  -std=c++2b (test for excess errors)
because the regex in dg-error was missing an indefinite article.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/103408
	* g++.dg/cpp23/auto-fncast11.C: Fix expected diagnostic wording.

On Tue, Dec 14, 2021 at 10:32:21AM -0700, Jeff Law wrote:
> I think the attached testcase should trigger on c6x with -mbig-endian -O2 -g

Thanks.  Finally I see what's going on.  c6x doesn't really need the CFA
with span > 1 (and I bet neither does armbe), the only reason why
dwf_cfa_reg is called is that the code in 13 cases just tries to compare
the CFA against dwf_cfa_reg (some_reg).  And that dwf_cfa_reg on some reg
that usually isn't a CFA reg results in targetm.dwarf_register_span hook
call, which on targets like c6x or armeb and others for some registers
creates a PARALLEL with various REGs in it, then the loop with the assertion
and finally operator== which just notes that the reg is different and fails.

This seems compile time memory and time inefficient.

The following so far untested patch instead adds an extra operator== and !=
for comparison of cfa_reg with rtx, which has the most common case where it
is a different register number done early without actually invoking
dwf_cfa_reg.  This means the assertion in dwf_cfa_reg can stay as is (at
least until some big endian target needs to have hard frame pointer or stack
pointer with span > 1 as well).
I've removed a different assertion there because it is redundant - dwf_regno
already has exactly that assertion in it too.

And I've included those 2 tweaks to avoid creating a REG in GC memory when
we can use {stack,hard_frame}_pointer_rtx which is already initialized to
the same REG we need by init_emit_regs.

On Tue, Dec 14, 2021 at 03:05:37PM -0700, Jeff Law wrote:
> So if someone is unfamiliar with the underlying issues here and needs to
> twiddle dwarf2cfi, how are they supposed to know if they should compare
> directly or use dwf_cfa_reg?

Comparison without dwf_cfa_reg should be used whenever possible, because
for registers which are never CFA related that won't call
targetm.dwarf_register_span uselessly.

The only comparisons with dwf_cfa_reg I've kept are the:
            regno = dwf_cfa_reg (XEXP (XEXP (dest, 0), 0));

            if (cur_cfa->reg == regno)
              offset -= cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == regno)
              offset -= cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == regno);
                offset -= cur_trace->cfa_temp.offset;
              }
and
            struct cfa_reg regno = dwf_cfa_reg (XEXP (dest, 0));

            if (cur_cfa->reg == regno)
              offset = -cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == regno)
              offset = -cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == regno);
                offset = -cur_trace->cfa_temp.offset;
              }
and there are 2 reasons for it:
1) there is an assertion, which guarantees it must compare equal to one of
those 3 cfa related struct cfa_reg structs, so it must be some CFA related
register (so, right now, targetm.dwarf_register_span shouldn't return
non-NULL in those on anything but gcn)
2) it is compared 3 times in a row, so for the GCN case doing
            if (cur_cfa->reg == XEXP (XEXP (dest, 0), 0))
              offset -= cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == XEXP (XEXP (dest, 0), 0))
              offset -= cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == XEXP (XEXP (dest, 0), 0));
                offset -= cur_trace->cfa_temp.offset;
              }
could actually create more GC allocated garbage than the way it is written
now.  But doing it that way would work fine.

I think for most of the comparisons even comparing with dwf_cfa_reg would
work but be less compile time/memory efficient (e.g. those assertions that
it is equal to some CFA related cfa_reg or in any spots where only the CFA
related regs may appear in the frame related patterns).

I'm aware just of a single spot where comparison with dwf_cfa_reg doesn't
work (when the assert is in dwf_cfa_reg), that is the spot that was ICEing
on your testcase, where we save arbitrary call saved register:
      if (REG_P (src)
          && REGNO (src) != STACK_POINTER_REGNUM
          && REGNO (src) != HARD_FRAME_POINTER_REGNUM
          && cur_cfa->reg == src)

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR debug/103619
	* dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert.
	(operator==, operator!=): New overloaded operators.
	(dwarf2out_frame_debug_adjust_cfa, dwarf2out_frame_debug_cfa_offset,
	dwarf2out_frame_debug_expr): Compare vars with cfa_reg type directly
	with REG rtxes rather than with dwf_cfa_reg results on those REGs.
	(create_cie_data): Use stack_pointer_rtx instead of
	gen_rtx_REG (Pmode, STACK_POINTER_REGNUM).
	(execute_dwarf2_frame): Use hard_frame_pointer_rtx instead of
	gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM).

	PR target/103661

gcc/ChangeLog:

	* config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0
	as API expects that non-zero values are returned (do that
	it mask == 31).
	For "avx512vbmi2" argument, we return now 1 << 31, which is a
	negative integer value.

On OMP_CLAUSEs we reuse TREE_TYPE as CP_OMP_CLAUSE_INFO in the C++ FE.
This confuses the hashing code that operand_equal_p does when checking.
There is really no reason to compare OMP_CLAUSEs against expressions
like captured this, they will never compare equal.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/103704
	* semantics.c (finish_omp_target_clauses_r): For OMP_CLAUSEs
	just walk subtrees.

	* g++.dg/gomp/pr103704.C: New test.

This patch uses the same not completely correct case insensitive comparisons
as used elsewhere in the same header.  Proper comparisons that would handle
even multi-byte characters would be harder, but I don't see them implemented
in __ctype's methods.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR libstdc++/71557
	* include/bits/locale_facets_nonio.tcc (_M_extract_via_format):
	Compare characters other than format specifiers and whitespace
	case insensitively.
	(_M_extract_name): Compare characters case insensitively.
	* testsuite/22_locale/time_get/get/char/71557.cc: New test.
	* testsuite/22_locale/time_get/get/wchar_t/71557.cc: New test.

Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand.

gcc/ChangeLog:

	PR target/101796
	* config/i386/predicates.md (const_vector_operand):
	Add new predicate.
	* config/i386/sse.md(<insn><mode>3<mask_name>):
	Add new define_split below.

gcc/testsuite/ChangeLog:

	PR target/101796
	* gcc.target/i386/pr101796-1.c: New test.

This patch implements XXSPLTIDP support for SF, and DF scalar constants.
The previous patch added support for vector constants.  This patch adds
the support for SFmode and DFmode scalar constants.

I added 2 new tests to test loading up SF and DF scalar constants.

2021-12-15  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
	(UNSPEC_XXSPLTIW_CONST): New unspec.
	(movsf_hardfloat): Add support for generating XXSPLTIDP.
	(mov<mode>_hardfloat32): Likewise.
	(mov<mode>_hardfloat64): Likewise.
	(xxspltidp_<mode>_internal): New insns.
	(xxspltiw_<mode>_internal): New insns.
	(splitters for SF/DFmode): Add new splitters for XXSPLTIDP.

gcc/testsuite/

	* gcc.target/powerpc/vec-splat-constant-df.c: New test.
	* gcc.target/powerpc/vec-splat-constant-sf.c: New test.

This patch implements XXSPLTIDP support for all vector constants.  The
XXSPLTIDP instruction is given a 32-bit immediate that is converted to a vector
of two DFmode constants.  The immediate is in SFmode format, so only constants
that fit as SFmode values can be loaded with XXSPLTIDP.

The constraint (eP) added in the previous patch for XXSPLTIW is also used
for XXSPLTIDP.

DImode scalar constants are not handled.  This is due to the majority of DImode
constants will be in the GPR registers.  With vector registers, you have the
problem that XXSPLTIDP splats the double word into both elements of the
vector.  However, if TImode is loaded with an integer constant, it wants a full
128-bit constant.

SFmode and DFmode scalar constants are not handled in this patch.  The
support for for those constants will be in the next patch.

I have added a temporary switch (-msplat-float-constant) to control whether or
not the XXSPLTIDP instruction is generated.

I added 2 new tests to test loading up V2DI and V2DF vector constants.

2021-12-14  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating XXSPLTIDP.
	(vsx_prefixed_constant): Likewise.
	(easy_vector_constant): Likewise.
	* config/rs6000/rs6000-protos.h (constant_generates_xxspltidp):
	New declaration.
	* config/rs6000/rs6000.c (output_vec_const_move): Add support for
	generating XXSPLTIDP.
	(prefixed_xxsplti_p): Likewise.
	(constant_generates_xxspltidp): New function.
	* config/rs6000/rs6000.opt (-msplat-float-constant): New debug option.

gcc/testsuite/

	* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
	regex for power10.
	* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.

This patch adds support to automatically generate the ISA 3.1 XXSPLTIW
instruction for V8HImode, V4SImode, and V4SFmode vectors.  It does this by
adding support for vector constants that can be used, and adding a
VEC_DUPLICATE pattern to generate the actual XXSPLTIW instruction.

Add the eP constraint to recognize constants that can be loaded into
vector registers with a single prefixed instruction such as xxspltiw and
xxspltidp.

I added 4 new tests to test loading up V16QI, V8HI, V4SI, and V4SF vector
constants.

2021-12-14  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/constraints.md (eP): Update comment.
	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating XXSPLTIW.
	(vsx_prefixed_constant): New predicate.
	(easy_vector_constant): Add support for
	generating XXSPLTIW.
	* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
	declaration.
	(constant_generates_xxspltiw): Likewise.
	* config/rs6000/rs6000.c (xxspltib_constant_p): Generate XXSPLTIW
	if possible instead of XXSPLTIB and sign extending the constant.
	(output_vec_const_move): Add support for XXSPLTIW.
	(prefixed_xxsplti_p): New function.
	(constant_generates_xxspltiw): New function.
	* config/rs6000/rs6000.md (prefixed attribute): Add support to
	mark XXSPLTI* instructions as being prefixed.
	* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
	switch.
	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
	generating XXSPLTIW or XXSPLTIDP.
	(vsx_mov<mode>_32bit): Likewise.
	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
	eP constraint.

gcc/testsuite/

	* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
	* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.

This patch adds support to generate the LXVKQ instruction to load specific
IEEE-128 floating point constants.

Compared to the last time I submitted this patch, I modified it so that it
uses the bit pattern of the vector to see if it can generate the LXVKQ
instruction.  This means on a little endian Power<xxx> system, the
following code will generate a LXVKQ 34,16 instruction:

    vector long long foo (void)
    {
      return (vector long long) { 0x0000000000000000, 0x8000000000000000 };
    }

because that vector pattern is the same bit pattern as -0.0F128.

2021-12-14  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/constraints.md (eQ): New constraint.
	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating the LXVKQ instruction.
	(easy_vector_constant_ieee128): New predicate.
	(easy_vector_constant): Add support for generating the LXVKQ
	instruction.
	* config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New
	declaration.
	* config/rs6000/rs6000.c (output_vec_const_move): Add support for
	generating LXVKQ.
	(constant_generates_lxvkq): New function.
	* config/rs6000/rs6000.opt (-mieee128-constant): New debug
	option.
	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
	generating LXVKQ.
	(vsx_mov<mode>_32bit): Likewise.
	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
	eQ constraint.

gcc/testsuite/

	* gcc.target/powerpc/float128-constant.c: New test.

This patch provides the data structure and function to convert a
CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a constant) to
an array of bytes, half-words, words, and  double words that can be loaded
into a 128-bit vector register.

The next patches will use this data structure to generate code that
generates load of the vector/floating point registers using the XXSPLTIDP,
XXSPLTIW, and LXVKQ instructions that were added in power10.

2021-12-15  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro.
	(VECTOR_128BIT_BYTES): Likewise.
	(VECTOR_128BIT_HALF_WORDS): Likewise.
	(VECTOR_128BIT_WORDS): Likewise.
	(VECTOR_128BIT_DOUBLE_WORDS): Likewise.
	(vec_const_128bit_type): New structure type.
	(vec_const_128bit_to_bytes): New declaration.
	* config/rs6000/rs6000.c (constant_int_to_128bit_vector): New
	helper function.
	(constant_fp_to_128bit_vector): New helper function.
	(vec_const_128bit_to_bytes): New function.

The conversion of a MEM address to ptr_mode in
try_store_by_multiple_pieces was misguided: copy_addr_to_reg expects
Pmode for addresses.


for  gcc/ChangeLog

	PR target/100518
	* builtins.c (try_store_by_multiple_pieces): Drop address
	conversion to ptr_mode.

for  gcc/testsuite/ChangeLog

	PR target/100518
	* gcc.target/aarch64/pr100518.c: New.

The testcase confuses the code that detects min and max len for the
memset, so max_len ends up less than min_len.  That shouldn't be
possible, but the testcase requires us to handle this case.

The store-by-mult-pieces algorithm actually relies on min and max
lengths, so if we find them to be inconsistent, the best we can do is
punting.


for  gcc/ChangeLog

	PR middle-end/100843
	* builtins.c (try_store_by_multiple_pieces): Fail if min_len
	is greater than max_len.

for  gcc/testsuite/ChangeLog

	PR middle-end/100843
	* gcc.dg/pr100843.c: New.

Check is_gimple_assign before gimple_assign_rhs_code.

gcc/ChangeLog:

	PR target/103682
	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
	is_gimple_assign before gimple_assign_rhs_code.

gcc/testsuite/ChangeLog:

	* gcc.c-torture/compile/pr103682.c: New test.

This checks whether the locale data for en_HK includes %p and adjusts
the string being tested accordingly. To account for Jakub's fix to make
%I parse "12" as 0 instead of 12, we need to change the expected value
for the case where the locale format doesn't include %p. Also change the
time from 12:00:00 to 12:02:01 so we can tell if the minutes and seconds
get mixed up.

libstdc++-v3/ChangeLog:

	PR libstdc++/103687
	* testsuite/22_locale/time_get/get_date/wchar_t/4.cc: Restore
	original locale before returning.
	* testsuite/22_locale/time_get/get_time/char/2.cc: Check for %p
	in locale's T_FMT and adjust accordingly.
	* testsuite/22_locale/time_get/get_time/wchar_t/2.cc: Likewise.

The stddef.h header checks/sets various hardcoded toolchain/os specific
macro guards to prevent redefining types such as ptrdiff_t, wchar_t, or
size_t. However, without this patch, the file does not check/set the
typedef macro guards for musl libc. This causes types such as size_t to
be defined twice for files which include both musl's stdlib.h as well as
GCC's ginclude/stddef.h. This is, for example, the case for
libgo/sysinfo.c. If libgo/sysinfo.c has multiple typedefs for size_t
this confuses -fdump-go-spec and causes size_t not to be included in the
generated type definitions thereby causing a gcc-go compilation failure
on Alpine Linux Edge (which uses musl libc) with the following error:

	sysinfo.go:7765:13: error: use of undefined type '_size_t'
	 7765 | type Size_t _size_t
	      |             ^
	libcall_posix.go:49:35: error: non-integer len argument in make
	   49 |                 b := make([]byte, len)
	      |

This commit fixes this issue by ensuring that ptrdiff_t, wchar_t, and size_t
are only defined once in the pre-processed libgo/sysinfo.c file by enhancing
gcc/ginclude/stddef.h with musl-specific typedef macro guards.

gcc/ChangeLog:

	* ginclude/stddef.h (__DEFINED_ptrdiff_t): Add support for musl
	libc typedef macro guard.
	(__DEFINED_size_t): Ditto.
	(__DEFINED_wchar_t): Ditto.

gcc/
	* regrename.c (find_rename_reg): Return satisfied regno
	if instruction is noop move.

std::regex currently allows invalid bracket ranges such as [\w-a] which
are only allowed by ECMAScript when in web browser compatibility mode.
It should be an error, because the start of the range is a character
class, not a single character. The current implementation of
_Compiler::_M_expression_term does not provide a way to reject this,
because we only remember a previous character, not whether we just
processed a character class (or collating symbol etc.)

This patch replaces the pair<bool, CharT> used to emulate
optional<CharT> with a custom class closer to pair<tribool,CharT>. That
allows us to track three states, so that we can tell when we've just
seen a character class.

With this additional state the code in _M_expression_term for processing
the _S_token_bracket_dash can be improved to correctly reject the [\w-a]
case, without regressing for valid cases such as [\w-] and [----].

libstdc++-v3/ChangeLog:

	PR libstdc++/102447
	* include/bits/regex_compiler.h (_Compiler::_BracketState): New
	class.
	(_Compiler::_BrackeyMatcher): New alias template.
	(_Compiler::_M_expression_term): Change pair<bool, CharT>
	parameter to _BracketState. Process first character for
	ECMAScript syntax as well as POSIX.
	* include/bits/regex_compiler.tcc
	(_Compiler::_M_insert_bracket_matcher): Pass _BracketState.
	(_Compiler::_M_expression_term): Use _BracketState to store
	state between calls. Improve handling of dashes in ranges.
	* testsuite/28_regex/algorithms/regex_match/cstring_bracket_01.cc:
	Add more tests for ranges containing dashes. Check invalid
	ranges with character class at the beginning.

libstdc++-v3/ChangeLog:

	* include/ext/pointer.h (_Relative_pointer_impl::_UIntPtrType):
	Rename to uintptr_t and define as __UINTPTR_TYPE__.

This removes the __syntax_option and __match_flag enumeration types,
which are only used to define enumerators with successive values that
are then used to initialize the std::regex_constants global variables.

By defining enumerators in the syntax_option_type and match_flag_type
enumeration types with the correct values for the globals we get rid of
two useless enumeration types that just count from 0 to N, and we
improve the debugging experience. Because the enumeration types now have
enumerators defined, GDB will print values in terms of those enumerators
e.g.

$6 = (std::regex_constants::_S_ECMAScript | std::regex_constants::_S_multiline)

Previously this would have been shown as simply 0x810 because there were
no enumerators of that type.

This changes the type and value of enumerators such as _S_grep, but
users should never be referring to them directly anyway.

libstdc++-v3/ChangeLog:

	* include/bits/regex_constants.h (__syntax_option, __match_flag):
	Remove.
	(syntax_option_type, match_flag_type): Define enumerators.
	Use to initialize globals. Add constexpr to compound assignment
	operators.
	* include/bits/regex_error.h (error_type): Add comment.
	* testsuite/28_regex/constants/constexpr.cc: Remove comment.
	* testsuite/28_regex/constants/error_type.cc: Improve comment.
	* testsuite/28_regex/constants/match_flag_type.cc: Check bitmask
	requirements.
	* testsuite/28_regex/constants/syntax_option_type.cc: Likewise.

While we had two sets of built-in infrastructure at once, I added _x as a
suffix to two arrays to disambiguate the old and new versions.  Time to fix
that also.

2021-12-06  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Rename
	rs6000_builtin_decls_x to rs6000_builtin_decls.
	(altivec_resolve_overloaded_builtin): Likewise.  Also rename
	rs6000_builtin_info_x to rs6000_builtin_info.
	* config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Rename
	rs6000_builtin_info_x to rs6000_builtin_info.
	(rs6000_builtin_is_supported): Likewise.
	(rs6000_gimple_fold_mma_builtin): Likewise.  Also rename
	rs6000_builtin_decls_x to rs6000_builtin_decls.
	(rs6000_gimple_fold_builtin): Rename rs6000_builtin_info_x to
	rs6000_builtin_info.
	(cpu_expand_builtin): Likewise.
	(rs6000_expand_builtin): Likewise.
	(rs6000_init_builtins): Likewise.  Also rename rs6000_builtin_decls_x
	to rs6000_builtin_decls.
	(rs6000_builtin_decl): Rename rs6000_builtin_decls_x to
	rs6000_builtin_decls.
	* config/rs6000/rs6000-gen-builtins.c (write_decls): In generated code,
	rename rs6000_builtin_decls_x to rs6000_builtin_decls, and rename
	rs6000_builtin_info_x to rs6000_builtin_info.
	(write_bif_static_init): In generated code, rename
	rs6000_builtin_info_x to rs6000_builtin_info.
	(write_init_bif_table): In generated code, rename
	rs6000_builtin_decls_x to rs6000_builtin_decls, and rename
	rs6000_builtin_info_x to rs6000_builtin_info.
	(write_init_ovld_table): In generated code, rename
	rs6000_builtin_decls_x to rs6000_builtin_decls.
	(write_init_file): Likewise.
	* config/rs6000/rs6000.c (rs6000_builtin_vectorized_function):
	Likewise.
	(rs6000_builtin_md_vectorized_function): Likewise.
	(rs6000_builtin_reciprocal): Likewise.
	(add_condition_to_bb): Likewise.
	(rs6000_atomic_assign_expand_fenv): Likewise.

While we had two sets of built-in functionality at the same time, I put "new"
in the names of quite a few functions.  Time to undo that.

2021-12-02  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-c.c (altivec_resolve_new_overloaded_builtin):
	Remove forward declaration.
	(rs6000_new_builtin_type_compatible): Rename to
	rs6000_builtin_type_compatible.
	(rs6000_builtin_type_compatible): Remove.
	(altivec_resolve_overloaded_builtin): Remove.
	(altivec_build_new_resolved_builtin): Rename to
	altivec_build_resolved_builtin.
	(altivec_resolve_new_overloaded_builtin): Rename to
	altivec_resolve_overloaded_builtin.  Remove static keyword.  Adjust
	called function names.
	* config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Remove
	forward declaration.
	(rs6000_gimple_fold_new_builtin): Likewise.
	(rs6000_invalid_new_builtin): Rename to rs6000_invalid_builtin.
	(rs6000_gimple_fold_builtin): Remove.
	(rs6000_new_builtin_valid_without_lhs): Rename to
	rs6000_builtin_valid_without_lhs.
	(rs6000_new_builtin_is_supported): Rename to
	rs6000_builtin_is_supported.
	(rs6000_gimple_fold_new_mma_builtin): Rename to
	rs6000_gimple_fold_mma_builtin.
	(rs6000_gimple_fold_new_builtin): Rename to
	rs6000_gimple_fold_builtin.  Remove static keyword.  Adjust called
	function names.
	(rs6000_expand_builtin): Remove.
	(new_cpu_expand_builtin): Rename to cpu_expand_builtin.
	(new_mma_expand_builtin): Rename to mma_expand_builtin.
	(new_htm_spr_num): Rename to htm_spr_num.
	(new_htm_expand_builtin): Rename to htm_expand_builtin.  Change name
	of called function.
	(rs6000_expand_new_builtin): Rename to rs6000_expand_builtin.  Remove
	static keyword.  Adjust called function names.
	(rs6000_new_builtin_decl): Rename to rs6000_builtin_decl.  Remove
	static keyword.
	(rs6000_builtin_decl): Remove.
	* config/rs6000/rs6000-gen-builtins.c (write_decls): In gnerated code,
	rename rs6000_new_builtin_is_supported to rs6000_builtin_is_supported.
	* config/rs6000/rs6000-internal.h (rs6000_invalid_new_builtin): Rename
	to rs6000_invalid_builtin.
	* config/rs6000/rs6000.c (rs6000_new_builtin_vectorized_function):
	Rename to rs6000_builtin_vectorized_function.
	(rs6000_new_builtin_md_vectorized_function): Rename to
	rs6000_builtin_md_vectorized_function.
	(rs6000_builtin_vectorized_function): Remove.
	(rs6000_builtin_md_vectorized_function): Remove.

2021-12-02  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-builtin.def: Delete.
	* config/rs6000/rs6000-call.c (builtin_compatibility): Delete.
	(builtin_description): Delete.
	(builtin_hash_struct): Delete.
	(builtin_hasher): Delete.
	(builtin_hash_table): Delete.
	(builtin_hasher::hash): Delete.
	(builtin_hasher::equal): Delete.
	(rs6000_builtin_info_type): Delete.
	(rs6000_builtin_info): Delete.
	(bdesc_compat): Delete.
	(bdesc_3arg): Delete.
	(bdesc_4arg): Delete.
	(bdesc_dst): Delete.
	(bdesc_2arg): Delete.
	(bdesc_altivec_preds): Delete.
	(bdesc_abs): Delete.
	(bdesc_1arg): Delete.
	(bdesc_0arg): Delete.
	(bdesc_htm): Delete.
	(bdesc_mma): Delete.
	(rs6000_overloaded_builtin_p): Delete.
	(rs6000_overloaded_builtin_name): Delete.
	(htm_spr_num): Delete.
	(rs6000_builtin_is_supported_p): Delete.
	(rs6000_gimple_fold_mma_builtin): Delete.
	(gt-rs6000-call.h): Remove include directive.
	* config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p): Delete.
	(rs6000_builtin_is_supported_p): Delete.
	(rs6000_overloaded_builtin_name): Delete.
	* config/rs6000/rs6000.c (rs6000_builtin_decls): Delete.
	(rs6000_debug_reg_global): Remove reference to RS6000_BUILTIN_COUNT.
	* config/rs6000/rs6000.h (rs6000_builtins): Delete.
	(altivec_builtin_types): Delete.
	(rs6000_builtin_decls): Delete.
	* config/rs6000/t-rs6000 (TM_H): Don't add rs6000-builtin.def.

2021-12-02  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-builtin-new.def: Rename to...
	* config/rs6000/rs6000-builtins.def: ...this.
	* config/rs6000/rs6000-gen-builtins.c: Adjust header commentary.
	* config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Rename
	rs6000-builtin-new.def to rs6000-builtins.def.
	(rs6000-builtins.c): Likewise.

2021-12-06  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Remove.
	* config/rs6000/rs6000.h (altivec_overloaded_builtins): Remove.

The compiler will gladly CSE the result of two __builtin_mma_build_acc
calls with the same four vector arguments, leading to illegal MMA
code being generated.  The fix here is to make the mma_assemble_acc
pattern use a unspec_volatile to stop the CSE from happening.

2021-12-14  Peter Bergner  <bergner@linux.ibm.com>

gcc/
	PR target/103548
	* config/rs6000/mma.md (UNSPEC_MMA_ASSEMBLE): Rename unspec from this...
	(UNSPEC_VSX_ASSEMBLE): ...to this.
	(UNSPECV_MMA_ASSEMBLE): New unspecv.
	(vsx_assemble_pair): Use UNSPEC_VSX_ASSEMBLE.
	(*vsx_assemble_pair): Likewise.
	(mma_assemble_acc): Use UNSPECV_MMA_ASSEMBLE.
	(*mma_assemble_acc): Likewise.
	* config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle
	UNSPEC_VOLATILE.  Use UNSPEC_VSX_ASSEMBLE and UNSPECV_MMA_ASSEMBLE.

gcc/testsuite/
	PR target/103548
	* gcc.target/powerpc/mma-builtin-10-pair.c: New test.
	* gcc.target/powerpc/mma-builtin-10-quad.c: New test.

gcc/fortran/ChangeLog:

	PR fortran/103717
	* frontend-passes.c (doloop_code): Prevent NULL pointer
	dereference when checking for passing a do-loop variable to a
	contained procedure with an interface mismatch.

gcc/testsuite/ChangeLog:

	PR fortran/103717
	* gfortran.dg/do_check_19.f90: New test.

gcc/fortran/ChangeLog:

	PR fortran/103718
	PR fortran/103719
	* frontend-passes.c (doloop_contained_procedure_code): Add several
	checks to prevent NULL pointer dereferences on valid and invalid
	code called within do-loops.

gcc/testsuite/ChangeLog:

	PR fortran/103718
	PR fortran/103719
	* gfortran.dg/do_check_18.f90: New test.

This is a preparation patch that moves VxHF vector set/insert/extract
expansions from AVX512FP16 ABI to lower ABIs.  There are no functional
changes for -mavx512fp16 and a follow-up patch is needed to actually
enable VxHF vector modes for lower ABIs.

2021-12-14  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	PR target/103571
	* config/i386/i386-expand.c (ix86_expand_vector_init_duplicate)
	<case E_V8HFmode>: Implement for TARGET_SSE2.
	<case E_V16HFmode>: Implement for TARGET_AVX.
	<case E_V32HFmode>: Implement for TARGET_AVX512F.
	(ix86_expand_vector_set_var): Handle V32HFmode
	without TARGET_AVX512BW.
	(ix86_expand_vector_extract)
	<case E_V8HFmode>: Implement for TARGET_SSE2.
	<case E_V16HFmode>: Implement for TARGET_AVX.
	<case E_V32HFmode>: Implement for TARGET_AVX512BW.
	(expand_vec_perm_broadcast_1) <case E_V8HFmode>: New.
	* config/i386/sse.md (VI12HF_AVX512VL): Remove
	TARGET_AVX512FP16 condition.
	(V): Ditto.
	(V_256_512): Ditto.
	(avx_vbroadcastf128_<mode>): Use V_256H mode iterator.

To allow for a sane switch-over from the old built-in infrastructure to the
new, both sets of code have co-existed, with the enabled one under the control
of the boolean variable new_builtins_are_live.  As a first step in removing the
old code, remove this variable and the now-dead code it was guarding.

2021-12-06  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Remove
	test for new_builtins_are_live and simplify.
	* config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Remove
	dead function.
	(altivec_resolve_overloaded_builtin): Remove test for
	new_builtins_are_live and simplify.
	* config/rs6000/rs6000-call.c (altivec_init_builtins): Remove forward
	declaration.
	(builtin_function_type): Likewise.
	(rs6000_common_init_builtins): Likewise.
	(htm_init_builtins): Likewise.
	(mma_init_builtins): Likewise.
	(def_builtin): Remove dead function.
	(rs6000_expand_zeroop_builtin): Likewise.
	(rs6000_expand_mtfsf_builtin): Likewise.
	(rs6000_expand_mtfsb_builtin): Likewise.
	(rs6000_expand_set_fpscr_rn_builtin): Likewise.
	(rs6000_expand_set_fpscr_drn_builtin): Likewise.
	(rs6000_expand_unop_builtin): Likewise.
	(altivec_expand_abs_builtin): Likewise.
	(rs6000_expand_binop_builtin): Likewise.
	(altivec_expand_lxvr_builtin): Likewise.
	(altivec_expand_lv_builtin): Likewise.
	(altivec_expand_stxvl_builtin): Likewise.
	(altivec_expand_stv_builtin): Likewise.
	(mma_expand_builtin): Likewise.
	(htm_expand_builtin): Likewise.
	(cpu_expand_builtin): Likewise.
	(rs6000_expand_quaternop_builtin): Likewise.
	(rs6000_expand_ternop_builtin): Likewise.
	(altivec_expand_dst_builtin): Likewise.
	(altivec_expand_vec_sel_builtin): Likewise.
	(altivec_expand_builtin): Likewise.
	(rs6000_invalid_builtin): Likewise.
	(rs6000_builtin_valid_without_lhs): Likewise.
	(rs6000_gimple_fold_builtin): Remove test for new_builtins_are_live and
	simplify.
	(rs6000_expand_builtin): Likewise.
	(rs6000_init_builtins): Remove tests for new_builtins_are_live and
	simplify.
	(rs6000_builtin_decl): Likewise.
	(altivec_init_builtins): Remove dead function.
	(mma_init_builtins): Likewise.
	(htm_init_builtins): Likewise.
	(builtin_quaternary_function_type): Likewise.
	(builtin_function_type): Likewise.
	(rs6000_common_init_builtins): Likewise.
	* config/rs6000/rs6000-gen-builtins.c (write_header_file): Don't
	declare new_builtins_are_live.
	(write_init_bif_table): In generated code, remove test for
	new_builtins_are_live and simplify.
	(write_init_ovld_table): Likewise.
	(write_init_file): Don't initialize new_builtins_are_live.
	* config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): Remove
	test for new_builtins_are_live and simplify.
	(rs6000_builtin_md_vectorized_function): Likewise.
	(rs6000_builtin_reciprocal): Likewise.
	(add_condition_to_bb): Likewise.
	(rs6000_atomic_assign_expand_fenv): Likewise.

2021-12-13  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	PR target/103625
	* config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vcmpequd):
	Move to power8-vector stanza.
	(__builtin_altivec_vcmpequd_p): Likewise.
	(__builtin_altivec_vcmpgtsd): Likewise.
	(__builtin_altivec_vcmpgtsd_p): Likewise.
	(__builtin_altivec_vcmpgtud): Likewise.
	(__builtin_altivec_vcmpgtud_p): Likewise.

2021-12-14  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	PR target/103623
	* config/rs6000/rs6000-builtin-new.def (__builtin_pack_longdouble): Add
	ibmld attribute.
	(__builtin_unpack_longdouble): Likewise.
	* config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Add special
	handling for ibmld attribute.
	* config/rs6000/rs6000-gen-builtins.c (attrinfo): Add isibmld.
	(parse_bif_attrs): Handle ibmld.
	(write_decls): Likewise.
	(write_bif_static_init): Likewise.

This patch adds support for initialization of global variables
with rvalues and creating constructors for array, struct and
union types which can be used as rvalues.

Signed-off-by:
2021-12-14	Petter Tomner	<tomner@kth.se>

gcc/jit/
	* jit-common.h: New enum
	* jit-playback.c : Folding an setting intitial
	(global_new_decl) : Handle const global generation
	(new_global) : New flag
	(global_set_init_rvalue) : New
	(new_ctor) : New
	(new_global_initialized) : Flag
	(as_truth_value) : Fold
	(new_unary_op) : Fold
	(new_binary_op) : Fold
	(new_comparison) : Fold
	(new_array_access) : Fold
	(new_dereference) : Fold
	(get_address) : Fold
	* jit-playback.h :
	(global_set_init_rvalue) : New
	(new_ctor) : New
	* jit-recording.c :
	* jit-recording.h :
	(new_global_init_rvalue) : New
	(new_ctor) : New
	(ctor) : New, inherits rvalue
	(global_init_rvalue) : New, inherits memento
	(type::is_union) : New
	* libgccjit++.h : New entrypoints, see C-header
	* libgccjit.c : See .h
	* libgccjit.h : New entrypoints
	(gcc_jit_context_new_array_constructor) : New
	(gcc_jit_context_new_struct_constructor) : New
	(gcc_jit_context_new_union_constructor) : New
	(gcc_jit_global_set_initializer_rvalue) : New
	(LIBGCCJIT_HAVE_CTORS) : New feuture macro
	* libgccjit.map : New entrypoints added to ABI 19
	* docs/topics/expressions.rst : Updated docs

gcc/testsuite/
	* jit.dg/all-non-failing-tests.h: Added two tests
	* jit.dg/test-error-ctor-array-wrong-obj.c: New
	* jit.dg/test-error-ctor-struct-too-big.c: New
	* jit.dg/test-error-ctor-struct-wrong-field-obj.c: New
	* jit.dg/test-error-ctor-struct-wrong-type.c: New
	* jit.dg/test-error-ctor-struct-wrong-type2.c
	* jit.dg/test-error-ctor-union-wrong-field-name.c: New
	* jit.dg/test-error-global-already-init.c: New
	* jit.dg/test-error-global-common-section.c: New
	* jit.dg/test-error-global-init-too-small-array.c: New
	* jit.dg/test-error-global-lvalue-init.c: New
	* jit.dg/test-error-global-nonconst-init.c: New
	* jit.dg/test-global-init-rvalue.c: New
	* jit.dg/test-local-init-rvalue.c: New