Import the new 2023d tzdata.zi file. The leapseconds file was also
updated to have a new expiry (no new leap seconds were added).

libstdc++-v3/ChangeLog:

	* src/c++20/tzdata.zi: Import new file from 2023d release.
	* src/c++20/tzdb.cc (tzdb_list::_Node::_S_read_leap_seconds)
	Update expiry date for leap seconds list.

The ICE on this testcase was fixed by r14-7141.

2024-01-15  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/113048
	* gcc.target/i386/pr113048.c: New test.

gcc/
	* doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, clmul_si,
brev8_si are both included in rv32 and rv64. Test them in scalar_bitmanip_intrinsic-64-emulated.c.

gcc/ChangeLog:

	* config.gcc: Include riscv_bitmanip.h.
	* config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
	* config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
	* config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
	(RISCV_BUILTIN_NO_PREFIX): New helper macro.
	* config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
	* config/riscv/riscv-ftypes.def (2): New ftypes.
	* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
	(RISCV_BUILTIN_NO_PREFIX): Likewise.
	* config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
	* gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c: New test.
	* gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

	* config.gcc: Include riscv_crypto.h.
	* config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
	* gcc.target/riscv/scalar_crypto_intrinsic-64.c: New test.

The serials patch provides a mapping from the RV intrinsics to the builtin names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites
that will be included in the intrinsic functions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb_32_bswap-2.c: Moved to...
	* gcc.target/riscv/zbb_bswap16.c: ...here.
	* gcc.target/riscv/zbkb32.c: Remove __builtin_riscv_(un)zip and
	zip,__builtin_riscv_brev8.
	* gcc.target/riscv/zbkb64.c: Remove __builtin_riscv_brev8.
	* gcc.target/riscv/zbb_32_bswap-1.c: Removed.
	* gcc.target/riscv/zbb_bswap-1.c: Removed.
	* gcc.target/riscv/zbb_bswap-2.c: Removed.
	* gcc.target/riscv/zbbw.c: Removed.
	* gcc.target/riscv/zbc32.c: Removed.
	* gcc.target/riscv/zbc64.c: Removed.
	* gcc.target/riscv/zbkc32.c: Removed.
	* gcc.target/riscv/zbkc64.c: Removed.
	* gcc.target/riscv/zbkx32.c: Removed.
	* gcc.target/riscv/zbkx64.c: Removed.
	* gcc.target/riscv/zknd32-2.c: Removed.
	* gcc.target/riscv/zknd64-2.c: Removed.
	* gcc.target/riscv/zkne32-2.c: Removed.
	* gcc.target/riscv/zkne64-2.c: Removed.
	* gcc.target/riscv/zknh-sha256-32.c: Removed.
	* gcc.target/riscv/zknh-sha256-64.c: Removed.
	* gcc.target/riscv/zknh-sha512-32.c: Removed.
	* gcc.target/riscv/zknh-sha512-64.c: Removed.
	* gcc.target/riscv/zksed32-2.c: Removed.
	* gcc.target/riscv/zksed64-2.c: Removed.
	* gcc.target/riscv/zksh32.c: Removed.
	* gcc.target/riscv/zksh64.c: Removed.

My recent patch for PR112918 triggered a hidden bug in LRA on MIPS.  A
pseudo is matched to a register constraint and assigned to a hard
registers at the first constraint sub-pass but later it is matched to
X constraint.  Keeping this pseudo in the register (MD0) prevents to
use the same register for another pseudo in the insn and this results
in LRA failure.  The patch fixes this by spilling the pseudo at the
constraint subpass when the chosen alternative constraint not require
hard register anymore.

gcc/ChangeLog:

	PR middle-end/113354
	* lra-constraints.cc (curr_insn_transform): Spill pseudo only used
	in the insn if the corresponding operand does not require hard
	register anymore.

	driver-avr.cc contains a spec that discriminates bwtween cores
	and devices by means of a mmcu=avr* spec pattern.  This does not
	work for new devices like AVR128* which also start with mmcu=avr
	like all cores do.  The patch uses a new spec function in order to
	tell apart cores from devices.

gcc/
	PR target/107201
	* config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
	* config/avr/driver-avr.cc (avr_no_devlib): New function.
	(avr_devicespecs_file): Use it to remove -nodevicelib from the
	options for cores only.
	* config/avr/avr-arch.h (avr_get_parch): New prototype.
	* config/avr/avr-devices.cc (avr_get_parch): New function.

This patch try to fix the bug when HAVE_ATOMIC_FETCH_ADD is
not defined in dec_waiting_unlocked function. As io.h does
not include async.h, the WRLOCK and RWUNLOCK macros are
undefined.

libgfortran/ChangeLog:

	* io/io.h (dec_waiting_unlocked): Use
	__gthread_rwlock_wrlock/__gthread_rwlock_unlock or
	__gthread_mutex_lock/__gthread_mutex_unlock functions
	to replace WRLOCK and RWUNLOCK macros.

Signed-off-by: Lipeng Zhu <lipeng.zhu@intel.com>

This patch fixes -70% performance drop from GCC-13.2 to GCC-14 with -march=rv64gcv in real hardware.

The root cause is incorrect cost model cause inefficient vectorization which makes us performance drop significantly.

So this patch does:

1. Adjust vector to scalar cost by introducing v to scalar reg move.
2. Adjust vec_construct cost since we does spend NUNITS instructions to construct the vector.

Tested on both RV32/RV64 no regression, Rebase to the trunk and commit it as it is approved by Robin.

	PR target/113247

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
	* config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
	* config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/reduc-19.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/vls/reduc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-21.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c: New test.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: New test.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-3.c: New test.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: New test.

Rebase in v3: Rebase to the trunk and commit it as it's approved by Robin.
Update in v2: Add dynmaic lmul test.

This patch fixes the regression between GCC 13.2.0 and trunk GCC (GCC-14)

GCC 13.2.0:

	lui	a5,%hi(a)
	li	a4,19
	sb	a4,%lo(a)(a5)
	li	a0,0
	ret

Trunk GCC:

        vsetvli a5,zero,e8,mf2,ta,ma
        li      a4,-32768
        vid.v   v1
        vsetvli zero,zero,e16,m1,ta,ma
        addiw   a4,a4,104
        vmv.v.i v3,15
        lui     a1,%hi(a)
        li      a0,19
        vsetvli zero,zero,e8,mf2,ta,ma
        vadd.vi v1,v1,1
        sb      a0,%lo(a)(a1)
        vsetvli zero,zero,e16,m1,ta,ma
        vzext.vf2       v2,v1
        vmv.v.x v1,a4
        vminu.vv        v2,v2,v3
        vsrl.vv v1,v1,v2
        vslidedown.vi   v1,v1,17
        vmv.x.s a0,v1
        snez    a0,a0
        ret

The root cause we are vectorizing the codes inefficiently since we doesn't cost len when NITERS < VF.
Leverage loop control of mask targets or rs6000 fixes the regression.

Tested no regression. Ok for trunk ?

	PR target/113281

gcc/ChangeLog:

	* config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
	(costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
	* config/riscv/riscv-vector-costs.h: New function.

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c: New test.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: New test.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c: New test.

The following avoids splitting an edge before redirecting it.  This
allows the loop father of the new block to be correct in the first
place.

	PR tree-optimization/113385
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	First redirect, then split the exit edge.

Notice the m_num_vector_iterations is not used, remove the redundant codes.

Committed.

gcc/ChangeLog:

	* config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
	Remove m_num_vector_iterations.
	* config/riscv/riscv-vector-costs.h: Ditto.

Add more dump check to robostify the tests.

Committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/reduc-1.c: Add dump check.
	* gcc.target/riscv/rvv/autovec/vls/reduc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/reduc-9.c: Ditto.

	Multilib options -mdouble= and -mlong-double= are not orthogonal:
	TARGET_HANDLE_OPTION = avr-common.cc::avr_handle_option() sets them
	such that  sizeof(double) <= sizeof(long double)  is always true.

gcc/
	PR target/113156
	* config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
	(-mbranch-cost): Set "Optimization" flag.

lower-bitint: Fix up handling of INTEGER_CSTs in handle_operand in right shifts or comparisons [PR113370]

The INTEGER_CST code uses the remainder bits in computations whether to use
whole constant or just part of it and extend it at runtime, and furthermore
uses it to avoid using all bits even when using the (almost) whole constant.
The problem is that the prec % (2 * limb_prec) computation it uses is
appropriate only for the normal lowering of mergeable operations (where
we process 2 limbs at a time in a loop starting with least significant
limbs and process the remaining 0-2 limbs after the loop (there with
constant indexes).  For that case it is ok not to emit the upper
prec % (2 * limb_prec) bits into the constant, because those bits will be
extracted using INTEGER_CST idx and so will be used directly in the
statements as INTEGER_CSTs.
For other cases, where we either process just a single limb in a loop,
process it downwards (e.g. non-equality comparisons) or with some runtime
addends (some shifts), there is either just at most one limb lowered with
INTEGER_CST idx after the loop (e.g. for right shift) or before the loop
(e.g. non-equality comparisons), or all limbs are processed with
non-INTEGER_CST indexes (e.g. for left shift, when m_var_msb is set).
Now, the m_var_msb case is already handled through
              if (m_var_msb)
                type = TREE_TYPE (op);
              else
                /* If we have a guarantee the most significant partial limb
                   (if any) will be only accessed through handle_operand
                   with INTEGER_CST idx, we don't need to include the partial
                   limb in .rodata.  */
                type = build_bitint_type (prec - rem, 1);
but for the right shifts or comparisons the prec - rem when rem was
prec % (2 * limb_prec) was incorrect, so the following patch fixes it
to use remainder for 2 limbs only if m_upwards_2limb and remainder for
1 limb otherwise.

2024-01-15  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113370
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
	set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
	set it to just prec % limb_prec.

	* gcc.dg/torture/bitint-48.c: New test.

This patch fixes the following FAILs:

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.c-torture/execute/pr68532.c   -O0  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none  execution test

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

The root cause is attributes of ternary intructions are incorrect which cause AVL prop PASS and VSETVL PASS behave
incorrectly.

Tested no regression and committed.

	PR target/113393

gcc/ChangeLog:

	* config/riscv/vector.md: Fix ternary attributes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr113393-1.c: New test.
	* gcc.target/riscv/rvv/autovec/pr113393-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr113393-3.c: New test.

PIC/abicalls option will generate some GOT operation, and some
`ld/sd` instructions are used.

Let's skip them.

gcc/testsuite
	* gcc.target/mips/unaligned-2.c: Add -mno-abicalls option.

hppa*-*-hpux* doesn't have strdup or strndup.

2024-01-14  John David Anglin  <danglin@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	* gcc.dg/builtin-object-size-1.c: Disable tests for strdup/strndup
	on __hpux__.
	* gcc.dg/builtin-object-size-2.c: Likewise.
	* gcc.dg/builtin-object-size-3.c: Likewise.
	* gcc.dg/builtin-object-size-4.c: Likewise.

hppa*-*-hpux* doesn't have strdup or strndup.

2024-01-14  John David Anglin  <danglin@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	* gcc.dg/builtin-dynamic-object-size-0.c: Skip on hppa*-*-hpux*.
	* gcc.dg/builtin-dynamic-object-size-1.c: Likewise.
	* gcc.dg/builtin-dynamic-object-size-2.c: Likewise.
	* gcc.dg/builtin-dynamic-object-size-3.c: Likewise.
	* gcc.dg/builtin-dynamic-object-size-4.c: Likewise.

2024-01-14  John David Anglin  <danglin@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	* gcc.dg/Wattributes-6.c: Fix dg-warning on hppa*64*-*-*.

2024-01-14  John David Anglin  <danglin@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	PR analyzer/113150
	* c-c++-common/analyzer/fd-glibc-byte-stream-socket.c: Skip
	on hppa*-*-hpux*.
	* c-c++-common/analyzer/fd-manpage-getaddrinfo-client.c: Likewise.
	* c-c++-common/analyzer/fd-mappage-getaddrinfo-server.c: Likewise.
	* c-c++-common/analyzer/fd-symbolic-socket.c: Likewise.
	* gcc.dg/analyzer/fd-glibc-byte-stream-connection-server.c: Likewise.

These devices see a 32 KiB block of their program memory (flash) in
the RAM address space.  This can be used to support .rodata in flash
provided Binutils support PR31124 (Add new emulations which locate
.rodata in flash).  This patch does the following:

* configure checks availability of Binutils PR31124.

* Add new command line options -mrodata-in-ram and -mflmap.
While -flmap is for internal usage (communicate hardware properties
from device-specs to the compiler proper), -mrodata-in-ram is a user
space option that allows to return to the current rodata-in-ram layout.

* Adjust gen-avr-mmcu-specs.cc so that device-specs are generated
that sanity check options, and that translate -m[no-]rodata-in-ram
to its emulation.

* Objects in .rodata don't drag __do_copy_data.

* Document new options and built-in macros.

	PR target/112944

gcc/
	* configure.ac [target=avr]: Check availability of emulations
	avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
	HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
	* configure: Regenerate.
	* config.in: Regenerate.
	* doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
	__AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.

	* config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
	* config/avr/avr-arch.h (enum avr_device_specific_features):
	Add AVR_ISA_FLMAP.
	* config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
	AVR_ISA_FLMAP.
	* config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
	(avr_set_core_architecture): Set avr_arch_index.
	(have_avrxmega2_flmap, have_avrxmega4_flmap)
	(have_avrxmega3_rodata_in_flash): Set new static const bool according
	to configure results.
	(avr_rodata_in_flash_p): New function using them.
	(avr_asm_init_sections): Let readonly_data_section->unnamed.callback
	track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
	(avr_asm_named_section): Track avr_has_rodata_p.
	(avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
	and not avr_rodata_in_flash_p ().
	* config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
	(LINK_SPEC): Add %(link_rodata_in_ram).
	(LINK_ARCH_SPEC): Remove.
	* config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
	(have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
	const bool according to configure results.
	(diagnose_mrodata_in_ram): New function.
	(print_mcu): Generate specs with the following changes:
	<*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
	need to extend avr/specs.h each time we add a new bell or whistle.
	<*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
	-m[no-]rodata-in-ram.
	<*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
	<*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
	<*cpp>: Add %(cpp_rodata_in_ram).
	<*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
	requested.
	<*self_spec>: Add -mflmap or %<mflmap as needed.

gcc/testsuite/
	* gcc.target/avr/torture/pr112944-flmap-0.c: New test.
	* gcc.target/avr/torture/pr112944-flmap-1.c: New test.

mips bootstraps have been broken for a while.  They've been triggering an error
about mutually exclusive equal-tests always being false when building
gencondmd.

This was ultimately tracked down to the ior<mode>3_mips16_asmacro pattern.  The
pattern uses the GPR mode iterator which looks like this:

(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])

The condition for the pattern looks like this:

  "ISA_HAS_MIPS16E2"

And if you dig into ISA_HAS_MIPS16E2:

/* The MIPS16e V2 instructions are available.  */
                                && !TARGET_64BIT)

The way the mode iterator is handled is by adding its condition to the
pattern's condition when we expand copies of the pattern resulting in this
condition for one of the two generated patterns:

(TARGET_MIPS16 && TARGET_MIPS16E2 && !TARGET_64BIT) && TARGET_64BIT

This can never be true because of the TARGET_64BIT tests.

The fix is trivial.  Don't use a mode iterator on that pattern.

Bootstrapped on mips64el.  I don't have any tests to compare against, so no
regression test data.

gcc/
	* config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
	not the GPR iterator.  Adjust pattern name and mode attribute
	accordingly.

gcc/fortran/ChangeLog:

	PR fortran/67277
	* trans-intrinsic.cc (gfc_conv_intrinsic_ishftc): Handle optional
	dummy argument for SIZE passed to ISHFTC.  Set default value to
	BIT_SIZE(I) when missing.

gcc/testsuite/ChangeLog:

	PR fortran/67277
	* gfortran.dg/ishftc_optional_size_1.f90: New test.

The hppa*64*-*-hpux* target is not included in the set of fortran_real_16
targets because it doesn't have cosl.  However, these tests don't need
cosl, etc.

2024-01-13  John David Anglin  <danglin@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	* gfortran.dg/fmt_f_default_field_width_3.f90: Add hppa*64*-*-hpux*
	to real_16 dg-error targets.
	* gfortran.dg/fmt_g_default_field_width_3.f90: Likewise.

gcc/fortran/ChangeLog:

	PR fortran/113305
	* gfortran.h (gfc_loop_annot): New.
	(gfc_iterator, gfc_forall_iterator): Use for annotation control.
	* array.cc (gfc_copy_iterator): Adjust.
	* gfortran.texi: Document annotations IVDEP, UNROLL n, VECTOR,
	NOVECTOR as applied to DO CONCURRENT.
	* parse.cc (parse_do_block): Parse annotations IVDEP, UNROLL n,
	VECTOR, NOVECTOR as applied to DO CONCURRENT.  Apply UNROLL only to
	first loop control variable.
	* trans-stmt.cc (iter_info): Use gfc_loop_annot.
	(gfc_trans_simple_do): Adjust.
	(gfc_trans_forall_loop): Annotate loops with IVDEP, UNROLL n,
	VECTOR, NOVECTOR as needed for DO CONCURRENT.
	(gfc_trans_forall_1): Handle loop annotations.

gcc/testsuite/ChangeLog:

	PR fortran/113305
	* gfortran.dg/do_concurrent_7.f90: New test.

This is the last part of PR libstdc++/108822 implementing P2255R2, which
makes it ill-formed to create a std::tuple that would bind a reference
to a temporary.

The dangling checks are implemented as deleted constructors for C++20
and higher, and as Debug Mode static assertions in the constructor body
for older standards. This is similar to the r13-6084-g916ce577ad109b
changes for std::pair.

As part of this change, I've reimplemented most of std::tuple for C++20,
making use of concepts to replace the enable_if constraints, and using
conditional explicit to avoid duplicating most constructors. We could
use conditional explicit for the C++11 implementation too (with pragmas
to disables the -Wc++17-extensions warnings), but that should be done as
a stage 1 change for GCC 15 rather than now.

The partial specialization for std::tuple<T1, T2> is no longer used for
C++20 (or more precisely, for a C++20 compiler that supports concepts
and conditional explicit). The additional constructors and assignment
operators that take std::pair arguments have been added to the C++20
implementation of the primary template, with sizeof...(_Elements)==2
constraints. This avoids reimplementing all the other constructors in
the std::tuple<T1, T2> partial specialization to use concepts. This way
we avoid four implementations of every constructor and only have three!
(The primary template has an implementation of each constructor for
C++11 and another for C++20, and the tuple<T1,T2> specialization has an
implementation of each for C++11, so that's three for each constructor.)

In order to make the constraints more efficient on the C++20 version of
the default constructor I've also added a variable template for the
__is_implicitly_default_constructible trait, implemented using concepts.

libstdc++-v3/ChangeLog:

	PR libstdc++/108822
	* include/std/tuple (tuple): Add checks for dangling references.
	Reimplement constraints and constant expressions using C++20
	features.
	* include/std/type_traits [C++20]
	(__is_implicitly_default_constructible_v): Define.
	(__is_implicitly_default_constructible): Use variable template.
	* testsuite/20_util/tuple/dangling_ref.cc: New test.

Reviewed-by: Patrick Palka <ppalka@redhat.com>

As the testcase shows, the INTEGER_CST handling in handle_operand_addr
(i.e. what is used when passing address of an integer to a bitint library
routine) wasn't correct.  If the minimum precision to represent an
INTEGER_CST is smaller or equal to limb_prec, the code correctly uses
m_limb_type; if the minimum precision of a _BitInt INTEGER_CST is large
enough such that the bitint is middle, large or huge, everything is fine
too.  But the code wasn't handling correctly e.g. __int128 constants which
need more than limb_prec bits or _BitInt constants which on the architecture
are considered small (say have DImode limb_mode, TImode abi_limb_mode and
for [65, 128] bits use TImode scalar like the proposed aarch64 patch).
Best would be to use an array of 2/3/4 limbs in that case, but we'd need to
convert the INTEGER_CST to a CONSTRUCTOR in the right endianity etc.,
so the code was using mid_min_prec to enforce a middle _BitInt precision.
Except that mid_min_prec can be 0 and not computed yet, or it doesn't have
to be the smallest middle _BitInt precision, just the smallest so far
encountered.  So, on the testcase one possibility was that it used precision
65 from mid_min_prec, even when the INTEGER_CST actually needed larger
minimum precision (96 bits at least), or crashed when mid_min_prec was 0.

The patch fixes it in 2 hunks, the first makes sure we actually try to
create a BITINT_TYPE for the > limb_prec cases like __int128, and the second
instead of using mid_min_prec attempts to increase mp precision until it
isn't small anymore.

2024-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113361
	* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
	Fix up determination of the type for > limb_prec constants.

	* gcc.dg/torture/bitint-47.c: New test.

When the testcase was being adjusted for unsigned long -> unsigned long long,
two spots using long weren't changed to long long, so the testcase still warns
about UB in shifts.

2024-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113287
	* gcc.dg/vect/vect-early-break_100-pr113287.c: Use long long instead
	of long.

The following patch attempts to implement what apparently clang++
implemented for explicit object member function mangling, but nobody
actually proposed in patch form in
https://github.com/itanium-cxx-abi/cxx-abi/issues/148

2024-01-13  Jakub Jelinek  <jakub@redhat.com>

gcc/cp/
	* mangle.cc (write_nested_name): Mangle explicit object
	member functions with H as per
	https://github.com/itanium-cxx-abi/cxx-abi/issues/148 non-proposal.
gcc/testsuite/
	* g++.dg/abi/mangle79.C: New test.
include/
	* demangle.h (enum demangle_component_type): Add
	DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION.
libiberty/
	* cp-demangle.c (FNQUAL_COMPONENT_CASE): Add case for
	DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION.
	(d_dump): Handle DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION.
	(d_nested_name): Parse H after N in nested name.
	(d_count_templates_scopes): Handle
	DEMANGLE_COMPONENT_XOBJ_MEMBER_FUNCTION.
	(d_print_mod): Likewise.
	(d_print_function_type): Likewise.
	* testsuite/demangle-expected: Add tests for explicit object
	member functions.

Adds a few new testcases for some missed optimization regressions.
The analysis on how each should be optimized is in the testcases
themselves (and in the bug report).

Committed as obvious after running the testsuite to make sure they pass.

	PR tree-optimization/107823
	PR tree-optimization/110768
	PR tree-optimization/110941
	PR tree-optimization/110450
	PR tree-optimization/110841

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/ssa-thread-22.c: New test.
	* gcc.dg/tree-ssa/vrp-loop-1.c: New test.
	* gcc.dg/tree-ssa/vrp-loop-2.c: New test.
	* gcc.dg/tree-ssa/vrp-unreachable-1.c: New test.
	* gcc.dg/tree-ssa/vrp-unreachable-2.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

The implementation is based off of std::bind_front.  Since this is a
C++23 feature we use deducing this unconditionally.

	PR libstdc++/108827
	PR libstdc++/111327

libstdc++-v3/ChangeLog:

	* include/bits/version.def (bind_back): Define.
	* include/bits/version.h: Regenerate.
	* include/std/functional (_Bind_back): Define for C++23.
	(bind_back): Likewise.
	* testsuite/20_util/function_objects/bind_back/1.cc: New test
	(adapted from corresponding bind_front test).
	* testsuite/20_util/function_objects/bind_back/111327.cc: Likewise.

This simplifies the operator() of _Bind_front using C++23 deducing
this, allowing us to condense multiple operator() overloads into one.

In passing I think we can remove _Bind_front's defaulted special member
declarations and just let the compiler implicitly generate them for us.

libstdc++-v3/ChangeLog:

	* include/std/functional (_Bind_front): Remove =default special
	member function declarations.
	(_Bind_front::operator()): Implement using C++23 deducing this
	when available.
	* testsuite/20_util/function_objects/bind_front/111327.cc:
	Adjust testcase to expect better errors in C++23 mode.

This avoids redundant moves when composing and partially applying range
adaptor objects.

libstdc++-v3/ChangeLog:

	* include/std/ranges (views::__adaptor::operator|): Perform
	perfect forwarding of arguments.
	(views::__adaptor::_RangeAdaptor::operator()): Pass dummy
	first argument to _Partial.
	(views::__adaptor::_Partial::_Partial): Likewise.  Add dummy
	first parameter.
	(views::__adaptor::_Pipe::_Pipe): Perform perfect forwarding
	of arguments.
	(to): Pass dummy first argument to _Partial.

I implemented the resolution of LWG 3809 in r13-4364-ga64775a0edd469 but
it was recently noted in the MSVC STL github repo that the change causes
possible truncation for 64-bit seeds. Whether the truncation occurs (and
to what value) depends on the width of uint_least32_t which is not
portable, so the output of the PRNG for 64-bit seed values is no longer
the same as in C++20, and no longer portable across platforms.

That new issue was filed as LWG 4014. I proposed a new change which
reduces the seed by the LCG's modulus before the conversion to
uint_least32_t. This ensures that 64-bit seed values are consistently
reduced by the modulus before any truncation. This removes the
platform-dependent behaviour and restores the old behaviour for
std::subtract_with_carry_engine specializations using a 64-bit result
type (such as std::ranlux48_base).

libstdc++-v3/ChangeLog:

	PR libstdc++/107466
	* include/bits/random.tcc (subtract_with_carry_engine::seed):
	Implement proposed resolution of LWG 4014.
	* testsuite/26_numerics/random/pr60037-neg.cc: Adjust dg-error
	line number.
	* testsuite/26_numerics/random/subtract_with_carry_engine/cons/lwg3809.cc:
	Check for expected result of 64-bit engine with seed that
	doesn't fit in 32-bits.

gcc/
	* doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
	Add web-link to the avr-gcc wiki.