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  1. Jan 20, 2025
    • Giuseppe D'Angelo's avatar
      libstdc++: perfectly forward std::ranges::clamp arguments · b3426141
      Giuseppe D'Angelo authored
      
      As reported in PR118185, std::ranges::clamp does not correctly forward
      the projected value to the comparator. Add the missing forward.
      
      libstdc++-v3/ChangeLog:
      
      	PR libstdc++/118185
      	PR libstdc++/100249
      	* include/bits/ranges_algo.h (__clamp_fn): Correctly forward the
      	projected value to the comparator.
      	* testsuite/25_algorithms/clamp/118185.cc: New test.
      
      Signed-off-by: default avatarGiuseppe D'Angelo <giuseppe.dangelo@kdab.com>
      Reviewed-by: default avatarPatrick Palka <ppalka@redhat.com>
      Reviewed-by: default avatarJonathan Wakely <jwakely@redhat.com>
      b3426141
    • Christophe Lyon's avatar
      arm, testsuite: fix fast-math-bb-slp-complex-mla-float.c dg-add-options · 7cc57301
      Christophe Lyon authored
      The test uses floats, not fp16 so it should use arm_v8_3a_complex_neon
      instead of arm_v8_3a_fp16_complex_neon.
      
      This makes it PASS on arm-linux-gnueabihf instead of being UNRESOLVED.
      
      	gcc/testsuite/ChangeLog:
      	* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c: Use
      	arm_v8_3a_complex_neon.
      7cc57301
    • Christophe Lyon's avatar
      arm, testsuite: remove duplicate dg-add-options arm_v8_3a_complex_neon · cb356512
      Christophe Lyon authored
      These two testcases have twice the same dg-add-options
      arm_v8_3a_complex_neon, the patch removes one of them.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.dg/vect/complex/complex-operations-run.c: Remove duplicate
      	dg-add-options arm_v8_3a_complex_neon.
      	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-double.c:
      	Likewise.
      cb356512
    • Richard Biener's avatar
      tree-optimization/117875 - missed SLP vectorization · 7b64f757
      Richard Biener authored
      There's a discrepancy in SLP vs non-SLP vectorization that SLP build
      does not handle plain SSA copies (which should have been elimiated
      earlier).  But this now bites back since non-SLP happily handles them,
      causing a regression with --param vect-force-slp=1 which is now default,
      resulting in a big performance regression in 456.hmmer.
      
      So the following restores parity between SLP and non-SLP here, defering
      the missed copy elimination to later (PR118565).
      
      	PR tree-optimization/117875
      	* tree-vect-slp.cc (vect_build_slp_tree_1): Handle SSA copies.
      7b64f757
    • Xi Ruoyao's avatar
      LoongArch: Improve reassociation for bitwise operation and left shift [PR 115921] · 10e98638
      Xi Ruoyao authored
      For things like
      
              (x | 0x101) << 11
      
      It's obvious to write:
      
              ori     $r4,$r4,257
              slli.d  $r4,$r4,11
      
      But we are actually generating something insane:
      
              lu12i.w $r12,524288>>12             # 0x80000
              ori     $r12,$r12,2048
              slli.d  $r4,$r4,11
              or      $r4,$r4,$r12
              jr      $r1
      
      It's because the target-independent canonicalization was written before
      we have all the RISC targets where loading an immediate may need
      multiple instructions.  So for these targets we need to handle this in
      the target code.
      
      We do the reassociation on our own (i.e. reverting the
      target-independent reassociation) if "(reg [&|^] mask) << shamt" does
      not need to load mask into an register, and either:
      - (mask << shamt) needs to be loaded into an register, or
      - shamt is a const_immalsl_operand, so the outer shift may be further
        combined with an add.
      
      gcc/ChangeLog:
      
      	PR target/115921
      	* config/loongarch/loongarch-protos.h
      	(loongarch_reassoc_shift_bitwise): New function prototype.
      	* config/loongarch/loongarch.cc
      	(loongarch_reassoc_shift_bitwise): Implement.
      	* config/loongarch/loongarch.md
      	(*alslsi3_extend_subreg): New define_insn_and_split.
      	(<any_bitwise:optab>_shift_reverse<X:mode>): New
      	define_insn_and_split.
      	(<any_bitwise:optab>_alsl_reversesi_extended): New
      	define_insn_and_split.
      	(zero_extend_ashift): Remove as it's just a special case of
      	and_shift_reversedi, and it does not make too much sense to
      	write "alsl.d rd,rs,r0,shamt" instead of "slli.d rd,rs,shamt".
      	(bstrpick_alsl_paired): Remove as it is already done by
      	splitting and_shift_reversedi into and + ashift first, then
      	late combining the ashift and a further add.
      
      gcc/testsuite/ChangeLog:
      
      	PR target/115921
      	* gcc.target/loongarch/bstrpick_alsl_paired.c (scan-rtl-dump):
      	Scan for and_shift_reversedi instead of the removed
      	bstrpick_alsl_paired.
      	* gcc.target/loongarch/bitwise-shift-reassoc.c: New test.
      10e98638
    • Xi Ruoyao's avatar
      LoongArch: Simplify using bstr{ins,pick} instructions for and · f3bedc9a
      Xi Ruoyao authored
      For bstrins, we can merge it into and<mode>3 instead of having a
      separate define_insn.
      
      For bstrpick, we can use the constraints to ensure the first source
      register and the destination register are the same hardware register,
      instead of emitting a move manually.
      
      This will simplify the next commit where we'll reassociate bitwise
      and left shift for better code generation.
      
      gcc/ChangeLog:
      
      	* config/loongarch/constraints.md (Yy): New define_constriant.
      	* config/loongarch/loongarch.cc (loongarch_print_operand):
      	For "%M", output the index of bits to be used with
      	bstrins/bstrpick.
      	* config/loongarch/predicates.md (ins_zero_bitmask_operand):
      	Exclude low_bitmask_operand as for low_bitmask_operand it's
      	always better to use bstrpick instead of bstrins.
      	(and_operand): New define_predicate.
      	* config/loongarch/loongarch.md (any_or): New
      	define_code_iterator.
      	(bitwise_operand): New define_code_attr.
      	(*<optab:any_or><mode:GPR>3): New define_insn.
      	(*and<mode:GPR>3): New define_insn.
      	(<optab:any_bitwise><mode:X>3): New define_expand.
      	(and<mode>3_extended): Remove, replaced by the 3rd alternative
      	of *and<mode:GPR>3.
      	(bstrins_<mode>_for_mask): Remove, replaced by the 4th
      	alternative of *and<mode:GPR>3.
      	(*<optab:any_bitwise>si3_internal): Remove, already covered by
      	the *<optab:any_or><mode:GPR>3 and *and<mode:GPR>3 templates.
      f3bedc9a
    • Xi Ruoyao's avatar
      testsuite: Fix name of PR116348 test case · 67b10ee8
      Xi Ruoyao authored
      gcc/testsuite/ChangeLog:
      
      	* gcc.c-torture/compile/pr116438.c: Rename to ...
      	* gcc.c-torture/compile/pr116348.c: ... this.
      67b10ee8
    • Richard Biener's avatar
      tree-optimization/118552 - failed LC SSA update after unrolling · 1265afa9
      Richard Biener authored
      When unrolling changes nesting relationship of loops we fail to
      mark blocks as in need to change for LC SSA update.  Specifically
      the LC SSA PHI on a former inner loop exit might be misplaced
      if that loop becomes a sibling of its outer loop.
      
      	PR tree-optimization/118552
      	* cfgloopmanip.cc (fix_loop_placement): Properly mark
      	exit source blocks as to be scanned for LC SSA update when
      	the loops nesting relationship changed.
      	(fix_loop_placements): Adjust.
      	(fix_bb_placements): Likewise.
      
      	* gcc.dg/torture/pr118552.c: New testcase.
      1265afa9
    • Thomas Schwinge's avatar
      nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib variant is built · 6c593799
      Thomas Schwinge authored
      For example, for GCC/nvptx built with '--with-arch=sm_52' (current default)
      and '--without-multilib-list', neither a sm_30 nor a sm_35 multilib variant
      is built, and thus no '-mptx=3.1' sub-variant either.  Such a configuration
      is possible as of commit 86b3a753
      "nvptx: Support '--with-multilib-list'", but currently results in the
      following bogus behavior:
      
          [...]/xgcc -print-multi-directory -mgomp -march=sm_52
          mgomp
          [...]/xgcc -print-multi-directory -mgomp -march=sm_35
          mgomp
          [...]/xgcc -print-multi-directory -mgomp -march=sm_30
          mgomp
          [...]/xgcc -print-multi-directory -mgomp -march=sm_35 -mptx=3.1
          .
          [...]/xgcc -print-multi-directory -mgomp -march=sm_30 -mptx=3.1
          .
      
      The latter two '.' are unexpected; linking OpenMP/nvptx offloading code
      like this fails with: 'unresolved symbol __nvptx_uni', for example.
      Instead of '.', the latter two should print 'mgomp', too.  To achieve that,
      we must not set up the '-mptx=3.1' multilib axis if no '-mptx=3.1'
      sub-variant is built.
      
      	gcc/
      	* config/nvptx/t-nvptx (MULTILIB_OPTIONS): Don't add 'mptx=3.1' if
      	neither sm_30 nor sm_35 multilib variant is built.
      6c593799
    • Jakub Jelinek's avatar
      tree, c++: Consider TARGET_EXPR invariant like SAVE_EXPR [PR118509] · d9d0eeea
      Jakub Jelinek authored
      My October PR117259 fix to get_member_function_from_ptrfunc to use a
      TARGET_EXPR rather than SAVE_EXPR unfortunately caused some regressions as
      well as the following testcase shows.
      What happens is that
      get_member_function_from_ptrfunc -> build_base_path calls save_expr,
      so since the PR117259 change in mnay cases it will call save_expr on
      a TARGET_EXPR.  And, for some strange reason a TARGET_EXPR is not considered
      an invariant, so we get a SAVE_EXPR wrapped around the TARGET_EXPR.
      That SAVE_EXPR <TARGET_EXPR <...>> gets initially added only to the second
      operand of ?:, so at that point it would still work fine during expansion.
      But unfortunately an expression with that subexpression is handed to the
      caller also through *instance_ptrptr = instance_ptr; and gets evaluated
      once again when computing the first argument to the method.
      So, essentially, we end up with
      (TARGET_EXPR <D.2907, ...>, (... ? ... SAVE_EXPR <TARGET_EXPR <D.2907, ...>
       ... : ...)) (... SAVE_EXPR <TARGET_EXPR <D.2907, ...> ..., ...);
      and while D.2907 is initialized during gimplification in the code dominating
      everything that uses it, the extra temporary created for the SAVE_EXPR
      is initialized only conditionally (if the ?: condition is true) but then
      used unconditionally, so we get
      pmf-4.C: In function ‘void foo(C, B*)’:
      pmf-4.C:12:11: warning: ‘<anonymous>’ may be used uninitialized [-Wmaybe-uninitialized]
         12 |   (y->*x) ();
            |   ~~~~~~~~^~
      pmf-4.C:12:11: note: ‘<anonymous>’ was declared here
         12 |   (y->*x) ();
            |   ~~~~~~~~^~
      diagnostic and wrong-code issue too.
      
      The following patch fixes it by considering a TARGET_EXPR invariant
      for SAVE_EXPR purposes the same as SAVE_EXPR is.  Really creating another
      temporary for it is just a waste of the IL.
      
      Unfortunately I had to tweak the omp matching code to be able to accept
      TARGET_EXPR the same as SAVE_EXPR.
      
      2025-01-20  Jakub Jelinek  <jakub@redhat.com>
      
      	PR c++/118509
      gcc/
      	* tree.cc (tree_invariant_p_1): Return true for TARGET_EXPR too.
      gcc/c-family/
      	* c-omp.cc (c_finish_omp_for): Handle TARGET_EXPR in first operand
      	of COMPOUND_EXPR incr the same as SAVE_EXPR.
      gcc/testsuite/
      	* g++.dg/expr/pmf-4.C: New test.
      d9d0eeea
    • Jakub Jelinek's avatar
      tree-ssa-dce: Fix calloc handling [PR118224] · d882e48d
      Jakub Jelinek authored
      As reported by Dimitar, this should have been a multiplication, but wasn't
      caught because in the test (~(__SIZE_TYPE__) 0) / 2 is the largest accepted
      size and so adding 3 to it also resulted in "overflow".
      
      The following patch adds one subtest to really verify it is a multiplication
      and fixes the operation.
      
      2025-01-20  Jakub Jelinek  <jakub@redhat.com>
      
      	PR tree-optimization/118224
      	* tree-ssa-dce.cc (is_removable_allocation_p): Multiply a1 by a2
      	instead of adding it.
      
      	* gcc.dg/pr118224.c: New test.
      d882e48d
    • Stefan Schulze Frielinghaus's avatar
      s390: Update vec_(load,store)_len(,_r) · 459816ef
      Stefan Schulze Frielinghaus authored
      Reflect latest updates for vec_(load,store)_len(,_r) which means that
      all types except character based types are deprecated.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_load_len): Deprecate
      	some overloads.
      	(s390_vec_store_len): Deprecate some overloads.
      	(s390_vec_load_len_r): Add.
      	(s390_vec_store_len_r): Add.
      	* config/s390/s390-c.cc (s390_vec_load_len_r): Add.
      	(s390_vec_store_len_r): Add.
      	* config/s390/vecintrin.h (vec_load_len_r): Redefine.
      	(vec_store_len_r): Redefine.
      459816ef
    • Stefan Schulze Frielinghaus's avatar
      s390: Vector shift: Add 128-bit integer support · 10c52b38
      Stefan Schulze Frielinghaus authored
      Add 128-bit vector shift support.  Deprecate vector shift by byte
      builtins where the shift amount is not of type unsigned character.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def: Add 128-bit variants.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/vector.md (<vec_shifts_name><mode>3): Add 128-bit
      	variants.
      	* config/s390/vx-builtins.md: Ditto.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/vector/vec-shift-10.c: New test.
      	* gcc.target/s390/vector/vec-shift-11.c: New test.
      	* gcc.target/s390/vector/vec-shift-12.c: New test.
      	* gcc.target/s390/vector/vec-shift-3.c: New test.
      	* gcc.target/s390/vector/vec-shift-4.c: New test.
      	* gcc.target/s390/vector/vec-shift-5.c: New test.
      	* gcc.target/s390/vector/vec-shift-6.c: New test.
      	* gcc.target/s390/vector/vec-shift-7.c: New test.
      	* gcc.target/s390/vector/vec-shift-8.c: New test.
      	* gcc.target/s390/vector/vec-shift-9.c: New test.
      10c52b38
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector maximum/minimum: Add 128-bit integer support · ec226016
      Stefan Schulze Frielinghaus authored
      For previous architectures emulate operation max/min.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def: Add 128-bit variants and remove
      	bool variants.
      	* config/s390/s390-builtin-types.def: Update accordinly.
      	* config/s390/s390.md: Emulate min/max for GPR.
      	* config/s390/vector.md: Add min/max patterns and emulate in
      	case of no VXE3.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/vector/vec-max-emu.c: New test.
      	* gcc.target/s390/vector/vec-min-emu.c: New test.
      ec226016
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector load positive: Add 128-bit integer support · 4cf5e261
      Stefan Schulze Frielinghaus authored
      For previous architectures emulate operation abs.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_abs_s128): Add.
      	(s390_vlpq): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/vector.md (abs<mode>2): Emulate w/o VXE3.
      	(*abs<mode>2): Add 128-bit variant.
      	(*vec_sel0<mode>): Make it a ...
      	(vec_sel0<mode>): named pattern.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/vector/vec-abs-emu.c: New test.
      4cf5e261
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector compare: Add 128-bit integer support · 2e87d6e4
      Stefan Schulze Frielinghaus authored
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def: Add 128-bit variants.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.cc (s390_expand_vec_compare_cc): Also
      	consider TI modes for vectors.
      	* config/s390/vector.md: Enable *vec_cmp et al. for VXE3.
      	* config/s390/vx-builtins.md: Ditto.
      2e87d6e4
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector devide/remainder · f31ddaaa
      Stefan Schulze Frielinghaus authored
      gcc/ChangeLog:
      
      	* config/s390/vector.md (div<mode>3): Add.
      	(udiv<mode>3): Add.
      	(mod<mode>3): Add.
      	(umod<mode>3): Add.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/vxe3/vd-1.c: New test.
      	* gcc.target/s390/vxe3/vd-2.c: New test.
      	* gcc.target/s390/vxe3/vdl-1.c: New test.
      	* gcc.target/s390/vxe3/vdl-2.c: New test.
      	* gcc.target/s390/vxe3/vr-1.c: New test.
      	* gcc.target/s390/vxe3/vr-2.c: New test.
      	* gcc.target/s390/vxe3/vrl-1.c: New test.
      	* gcc.target/s390/vxe3/vrl-2.c: New test.
      f31ddaaa
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Count leading/trailing zeros · 0f0b91ef
      Stefan Schulze Frielinghaus authored
      Add vector single element 128-bit integer support utilizing new
      instructions vclzq and vctzq.  Furthermore, add scalar 64-bit integer
      support utilizing new instructions clzg and ctzg.  For ctzg, also define
      the resulting value if the input operand equals zero.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_cntlz): Add 128-bit
      	integer overloads.
      	(s390_vclzq): Add.
      	(s390_vec_cnttz): Add 128-bit integer overloads.
      	(s390_vctzq): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.h (CTZ_DEFINED_VALUE_AT_ZERO): Define.
      	* config/s390/s390.md (*clzg): New insn.
      	(clztidi2): Exploit new insn for target arch15.
      	(ctzdi2): New insn.
      	* config/s390/vector.md (clz<mode>2): Extend modes including
      	128-bit integer.
      	(ctz<mode>2): Likewise.
      0f0b91ef
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector generate element masks · 41a69915
      Stefan Schulze Frielinghaus authored
      Add instruction vgem and vector builtins
      vec_gen_element_masks_{8,16,32,64,128}.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_gen_element_masks_128): Add.
      	(s390_vgemb): Add.
      	(s390_vgemh): Add.
      	(s390_vgemf): Add.
      	(s390_vgemg): Add.
      	(s390_vgemq): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.md (UNSPEC_VEC_VGEM): Add.
      	* config/s390/vecintrin.h (vec_gen_element_masks_8): Define.
      	(vec_gen_element_masks_16): Define.
      	(vec_gen_element_masks_32): Define.
      	(vec_gen_element_masks_64): Define.
      	(vec_gen_element_masks_128): Define.
      	* config/s390/vx-builtins.md (vgemv16qi): Add.
      	(vgem<mode>): Add.
      41a69915
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector eval · 7fb7b362
      Stefan Schulze Frielinghaus authored
      Add instruction veval and builtin vec_evaluate.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_evaluate): Add.
      	(s390_veval): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.md (UNSPEC_VEC_VEVAL): Add.
      	* config/s390/vecintrin.h (vec_evaluate): Define.
      	* config/s390/vector.md
      	(*veval<mode>_<logic_op1:logic_op_stringify><logic_op2:logic_op_stringify>):
      	Add.
      	(veval<mode>): Add.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/vxe3/veval-1.c: New test.
      	* gcc.target/s390/vxe3/veval-2.c: New test.
      	* gcc.target/s390/vxe3/veval-3.c: New test.
      	* gcc.target/s390/vxe3/veval-4.c: New test.
      	* gcc.target/s390/vxe3/veval-5.c: New test.
      	* gcc.target/s390/vxe3/veval-6.c: New test.
      	* gcc.target/s390/vxe3/veval-7.c: New test.
      	* gcc.target/s390/vxe3/veval-8.c: New test.
      	* gcc.target/s390/vxe3/veval-9.c: New test.
      7fb7b362
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Vector blend · adeb6ecc
      Stefan Schulze Frielinghaus authored
      Add instruction vblend and builtin vec_blend.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_vec_blend): Add.
      	(s390_vblendb): Add.
      	(s390_vblendh): Add.
      	(s390_vblendf): Add.
      	(s390_vblendg): Add.
      	(s390_vblendq): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.md (UNSPEC_VEC_VBLEND): Add.
      	* config/s390/vecintrin.h (vec_blend): Define.
      	* config/s390/vx-builtins.md (vblend<mode>): Add.
      adeb6ecc
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Bit deposit and extract · d71e20b8
      Stefan Schulze Frielinghaus authored
      Add instructions bdepg and bextg and corresponding builtins.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (s390_bdepg): Add.
      	(s390_bextg): Add.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/s390.md (UNSPEC_BDEPG): Add.
      	(UNSPEC_BEXTG): Add.
      	(bdepg): Add.
      	(bextg): Add.
      d71e20b8
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Load indexed address · 86a1acfd
      Stefan Schulze Frielinghaus authored
      Add instructions lxa and llxa.
      
      gcc/ChangeLog:
      
      	* config/s390/s390.md (*lxa<LXAMODE>_index): Add.
      	(*lxa<LXAMODE>_displacement_index): Add.
      	(*lxa<LXAMODE>_index_base): Add.
      	(*lxa<LXAMODE>_displacement_index_base): Add.
      	(*lxab_displacement_index_base): Add.
      	(*llxa<LXAMODE>_displacement_index): Add.
      	(*llxa<LXAMODE>_index_base): Add.
      	(*llxa<LXAMODE>_displacement_index_base): Add.
      	(*llxab_displacement_index_base): Add.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/llxa-1.c: New test.
      	* gcc.target/s390/llxa-2.c: New test.
      	* gcc.target/s390/llxa-3.c: New test.
      	* gcc.target/s390/lxa-1.c: New test.
      	* gcc.target/s390/lxa-2.c: New test.
      	* gcc.target/s390/lxa-3.c: New test.
      	* gcc.target/s390/lxa-4.c: New test.
      86a1acfd
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: New instruction variants supporting 128-bit integer · 447b917e
      Stefan Schulze Frielinghaus authored
      Add new instruction variants and also extend builtins in order to deal
      with 128-bit integer.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def: Add new instruction variants.
      	* config/s390/s390-builtin-types.def: Update accordingly.
      	* config/s390/vecintrin.h: Add new defines.
      	* config/s390/vector.md: Adapt insns for new instruction
      	variants.
      	* config/s390/vx-builtins.md: Ditto.
      447b917e
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Prepare for future builtins · b963174a
      Stefan Schulze Frielinghaus authored
      gcc/ChangeLog:
      
      	* config/s390/s390-builtins.def (B_VXE3): Define.
      	(B_ARCH15): Define.
      	* config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
      	Consistency checks for VXE3.
      	* config/s390/s390.cc (s390_expand_builtin): Consistency checks
      	for VXE3.
      
      gcc/testsuite/ChangeLog:
      
      	* lib/target-supports.exp: VXE3 effective target check.
      b963174a
    • Stefan Schulze Frielinghaus's avatar
      s390: Bump __VEC__ and add 128-bit integer zvector types · 13efa59c
      Stefan Schulze Frielinghaus authored
      Bump __VEC__ version to 10305 and add 128-bit integer vector types like
      `vector __int128` et al. to the zvector extension.
      
      gcc/ChangeLog:
      
      	* config/s390/s390-c.cc (rid_int128): New helper function.
      	(s390_macro_to_expand): Deal with `vector __int128`.
      	(s390_cpu_cpp_builtins_internal): Bump __VEC__.
      	* config/s390/s390.cc (s390_handle_vectorbool_attribute): Add
      	128-bit bool zvector.
      13efa59c
    • Stefan Schulze Frielinghaus's avatar
      s390: arch15: Prepare for a future architecture · a8192b59
      Stefan Schulze Frielinghaus authored
      gcc/ChangeLog:
      
      	* common/config/s390/s390-common.cc: Add arch15 processor flags.
      	* config.gcc: Add arch15 for options --with-{arch,mtune}.
      	* config/s390/driver-native.cc (s390_host_detect_local_cpu):
      	Default to arch15.
      	* config/s390/s390-opts.h (enum processor_type): Add
      	PROCESSOR_ARCH15.
      	* config/s390/s390.cc (processor_table,s390_issue_rate,
      	s390_get_sched_attrmask,s390_get_unit_mask): Add arch15.
      	* config/s390/s390.h (enum processor_flags): Add processor flags
      	for VXE3 and ARCH15.
      	(TARGET_CPU_VXE3): Define.
      	(TARGET_CPU_VXE3_P): Define.
      	(TARGET_CPU_ARCH15): Define.
      	(TARGET_CPU_ARCH15_P): Define.
      	(TARGET_VXE3): Define.
      	(TARGET_VXE3_P): Define.
      	(TARGET_ARCH15): Define.
      	(TARGET_ARCH15_P): Define.
      	* config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and
      	let attribute "enabled" deal with them.
      	* config/s390/s390.opt: Add arch15.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/s390/s390.exp: Set compiler flags for the vxe3
      	subdirectory of the testsuite as done e.g. for vxe2.
      a8192b59
    • Stefan Schulze Frielinghaus's avatar
      s390: Sort definitions in vecintrin.h · 2638aea4
      Stefan Schulze Frielinghaus authored
      gcc/ChangeLog:
      
      	* config/s390/vecintrin.h: Sort definitions.
      2638aea4
    • Stefan Schulze Frielinghaus's avatar
      s390: Stay scalar for TOINTVEC/tointvec · 0c6fdb9b
      Stefan Schulze Frielinghaus authored
      Currently TOINTVEC maps scalar mode TI/TF to vector mode V1TI/V1TF,
      respectively.  As a consequence we may end up with patterns with a
      mixture of scalar and vector modes as e.g. for
      
      (define_insn "vec_sel0<mode>"
        [(set (match_operand:VT 0 "register_operand" "=v")
              (if_then_else:VT
               (eq (match_operand:<TOINTVEC> 3 "register_operand" "v")
                   (match_operand:<TOINTVEC> 4 "const0_operand" ""))
               (match_operand:VT 1 "register_operand" "v")
               (match_operand:VT 2 "register_operand" "v")))]
      
      This is cumbersome since gen_vec_sel0ti() and gen_vec_sel0tf() require
      that operands 3 and 4 are of vector mode whereas the remainder of
      operands must be of scalar mode.  Likewise for tointvec.
      
      Fixed by staying scalar.
      
      gcc/ChangeLog:
      
      	* config/s390/vector.md: Stay scalar for TOINTVEC/tointvec.
      0c6fdb9b
    • Kito Cheng's avatar
      RISC-V: Add sifive_vector.h · 43a6001f
      Kito Cheng authored
      sifive_vector.h is a vendor specfic header, it should include before
      using sifive vector intrinsic, it's just include riscv_vector.h for now,
      we will separate the implementation by adding new pragma in future.
      
      gcc/ChangeLog:
      
      	* config.gcc (riscv*): Install sifive_vector.h.
      	* config/riscv/sifive_vector.h: New.
      43a6001f
    • Hongyu Wang's avatar
      i386: Fix wrong insn generated by shld/shrd ndd split [PR118510] · af4fb245
      Hongyu Wang authored
      For shld/shrd_ndd_2 insn, the spiltter outputs wrong pattern that
      mixed parallel for clobber and set. Use register_operand as dest
      and ajdust output template to fix.
      
      gcc/ChangeLog:
      
      	PR target/118510
      	* config/i386/i386.md (*x86_64_shld_ndd_2): Use register_operand
      	for operand[0] and adjust the output template to directly
      	generate ndd form shld pattern.
      	(*x86_shld_ndd_2): Likewise.
      	(*x86_64_shrd_ndd_2): Likewise.
      	(*x86_shrd_ndd_2): Likewise.
      
      gcc/testsuite/ChangeLog:
      
      	PR target/118510
      	* gcc.target/i386/pr118510.c: New test.
      af4fb245
    • GCC Administrator's avatar
      Daily bump. · a7185d9b
      GCC Administrator authored
      a7185d9b
  2. Jan 19, 2025
  3. Jan 18, 2025
    • Iain Buclaw's avatar
      d: Merge upstream dmd, druntime d115713410, phobos 1b242048c. · 2ead0129
      Iain Buclaw authored
      D front-end changes:
      
      	- Import latest fixes from dmd v2.110.0-rc.1.
      	- Integers in debug or version statements have been removed from
      	  the language.
      
      D runtime changes:
      
      	- Import latest fixes from druntime v2.110.0-rc.1.
      
      Phobos changes:
      
      	- Import latest fixes from phobos v2.110.0-rc.1.
      
      gcc/d/ChangeLog:
      
      	* dmd/MERGE: Merge upstream dmd d115713410.
      
      libphobos/ChangeLog:
      
      	* libdruntime/MERGE: Merge upstream druntime d115713410.
      	* src/MERGE: Merge upstream phobos 1b242048c.
      
      gcc/testsuite/ChangeLog:
      
      	* gdc.dg/asm3.d: Adjust test.
      2ead0129
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