In order to properly implement two-stage name lookup for dependent
operator expressions, we need to remember the result of unqualified
lookup of the operator at template definition time, and reuse that
result rather than performing another unqualified lookup at
instantiation time.

Ideally we could just store the lookup in the expression directly, but
as pointed out in r9-6405 this isn't really possible since we use the
standard tree codes to represent most dependent operator expressions.

We could perhaps create a new tree code to represent dependent operator
expressions, with enough operands to store the lookup along with
everything else, but that'd require a lot of careful work to make sure
we handle this new tree code properly across the frontend.

But currently type-dependent operator (and call) expressions are given
an empty TREE_TYPE, which dependent_type_p treats as dependent, so this
field is effectively unused except to signal that the expression is
type-dependent.  It'd be convenient if we could store the lookup there
while preserving the dependent-ness of the expression.

To that end, this patch creates a new kind of type, called
DEPENDENT_OPERATOR_TYPE, which we give to dependent operator expressions
and into which we can store the result of operator lookup at template
definition time (DEPENDENT_OPERATOR_TYPE_SAVED_LOOKUPS).  Since this
type is always dependent (by definition), and since the frontend doesn't
seem to care much about the exact type of a type-dependent expression,
using this type in place of a NULL_TREE type seems to "just work"; only
dependent_type_p and WILDCARD_TYPE_P need to be adjusted to return true
for this new type.

The rest of the patch mostly consists of adding the necessary plumbing
to pass DEPENDENT_OPERATOR_TYPE_SAVED_LOOKUPS to add_operator_candidates,
adjusting all callers of build_x_* appropriately, and removing the now
unnecessary push_operator_bindings mechanism.

In passing, this patch simplifies finish_constraint_binary_op to avoid
using build_x_binary_op for building a binary constraint-expr; we don't
need to consider operator overloads here, as the &&/|| inside a
constraint effectively always has the built-in meaning (since atomic
constraints must have bool type).

This patch also makes FOLD_EXPR_OP yield a tree_code instead of a raw
INTEGER_CST.

Finally, this patch adds the XFAILed test operator-8.C which is about
broken two-stage name lookup for rewritten non-dependent operator
expressions, an existing bug that's otherwise only documented in
build_new_op.

	PR c++/51577
	PR c++/83035
	PR c++/100465

gcc/cp/ChangeLog:

	* call.c (add_operator_candidates): Add lookups parameter.
	Use it to avoid performing a second unqualified lookup when
	instantiating a dependent operator expression.
	(build_new_op): Add lookups parameter and pass it appropriately.
	* constraint.cc (finish_constraint_binary_op): Use
	build_min_nt_loc instead of build_x_binary_op.
	* coroutines.cc (build_co_await): Adjust call to build_new_op.
	* cp-objcp-common.c (cp_common_init_ts): Mark
	DEPENDENT_OPERATOR_TYPE appropriately.
	* cp-tree.def (DEPENDENT_OPERATOR_TYPE): Define.
	* cp-tree.h (WILDCARD_TYPE_P): Accept DEPENDENT_OPERATOR_TYPE.
	(FOLD_EXPR_OP_RAW): New, renamed from ...
	(FOLD_EXPR_OP): ... this.  Change this to return the tree_code directly.
	(DEPENDENT_OPERATOR_TYPE_SAVED_LOOKUPS): Define.
	(templated_operator_saved_lookups): Define.
	(build_new_op): Add lookups parameter.
	(build_dependent_operator_type): Declare.
	(build_x_indirect_ref): Add lookups parameter.
	(build_x_binary_op): Likewise.
	(build_x_unary_op): Likewise.
	(build_x_compound_expr): Likewise.
	(build_x_modify_expr): Likewise.
	* cxx-pretty-print.c (get_fold_operator): Adjust after
	FOLD_EXPR_OP change.
	* decl.c (start_preparsed_function): Don't call
	push_operator_bindings.
	* decl2.c (grok_array_decl): Adjust calls to build_new_op.
	* method.c (do_one_comp): Likewise.
	(build_comparison_op): Likewise.
	* module.cc (trees_out::type_node): Handle DEPENDENT_OPERATOR_TYPE.
	(trees_in::tree_node): Likewise.
	* name-lookup.c (lookup_name): Revert r11-2876 change.
	(op_unqualified_lookup): Remove.
	(maybe_save_operator_binding): Remove.
	(discard_operator_bindings): Remove.
	(push_operator_bindings): Remove.
	* name-lookup.h (maybe_save_operator_binding): Remove.
	(push_operator_bindings): Remove.
	(discard_operator_bindings): Remove.
	* parser.c (cp_parser_unary_expression): Adjust calls to build_x_*.
	(cp_parser_binary_expression): Likewise.
	(cp_parser_assignment_expression): Likewise.
	(cp_parser_expression): Likewise.
	(do_range_for_auto_deduction): Likewise.
	(cp_convert_range_for): Likewise.
	(cp_parser_perform_range_for_lookup): Likewise.
	(cp_parser_template_argument): Likewise.
	(cp_parser_omp_for_cond): Likewise.
	(cp_parser_omp_for_incr): Likewise.
	(cp_parser_omp_for_loop_init): Likewise.
	(cp_convert_omp_range_for): Likewise.
	(cp_finish_omp_range_for): Likewise.
	* pt.c (fold_expression): Adjust after FOLD_EXPR_OP change. Pass
	templated_operator_saved_lookups to build_x_*.
	(tsubst_omp_for_iterator): Adjust call to build_x_modify_expr.
	(tsubst_expr) <case COMPOUND_EXPR>: Pass
	templated_operator_saved_lookups to build_x_*.
	(tsubst_copy_and_build) <case INDIRECT_REF>: Likewise.
	<case tcc_unary>: Likewise.
	<case tcc_binary>: Likewise.
	<case MODOP_EXPR>: Likewise.
	<case COMPOUND_EXPR>: Likewise.
	(dependent_type_p_r): Return true for DEPENDENT_OPERATOR_TYPE.
	* ptree.c (cxx_print_type): Handle DEPENDENT_OPERATOR_TYPE.
	* semantics.c (finish_increment_expr): Adjust call to
	build_x_unary_op.
	(finish_unary_op_expr): Likewise.
	(handle_omp_for_class_iterator): Adjust calls to build_x_*.
	(finish_omp_cancel): Likewise.
	(finish_unary_fold_expr): Use build_dependent_operator_type.
	(finish_binary_fold_expr): Likewise.
	* tree.c (cp_free_lang_data): Don't call discard_operator_bindings.
	* typeck.c (rationalize_conditional_expr): Adjust call to
	build_x_binary_op.
	(op_unqualified_lookup): Define.
	(build_dependent_operator_type): Define.
	(build_x_indirect_ref): Add lookups parameter and use
	build_dependent_operator_type.
	(build_x_binary_op): Likewise.
	(build_x_array_ref): Likewise.
	(build_x_unary_op): Likewise.
	(build_x_compound_expr_from_list): Adjust call to
	build_x_compound_expr.
	(build_x_compound_expr_from_vec): Likewise.
	(build_x_compound_expr): Add lookups parameter and use
	build_dependent_operator_type.
	(cp_build_modify_expr): Adjust call to build_new_op.
	(build_x_modify_expr): Add lookups parameter and use
	build_dependent_operator_type.
	* typeck2.c (build_x_arrow): Adjust call to build_new_op.

libcc1/ChangeLog:

	* libcp1plugin.cc (plugin_build_unary_expr): Adjust call to
	build_x_unary_op.
	(plugin_build_binary_expr): Adjust call to build_x_binary_op.

gcc/testsuite/ChangeLog:

	* g++.dg/lookup/operator-3.C: Split out operator overload
	declarations into ...
	* g++.dg/lookup/operator-3-ops.h: ... here.
	* g++.dg/lookup/operator-3a.C: New test.
	* g++.dg/lookup/operator-4.C: New test.
	* g++.dg/lookup/operator-4a.C: New test.
	* g++.dg/lookup/operator-5.C: New test.
	* g++.dg/lookup/operator-5a.C: New test.
	* g++.dg/lookup/operator-6.C: New test.
	* g++.dg/lookup/operator-7.C: New test.
	* g++.dg/lookup/operator-8.C: New test.

Enable VxHF vector modes for SSE2, AVX and AVX512F ABIs.

2021-12-16  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	PR target/103571
	* config/i386/i386.h (VALID_AVX256_REG_MODE): Add V16HFmode.
	(VALID_AVX256_REG_OR_OI_VHF_MODE): Replace with ...
	(VALID_AVX256_REG_OR_OI_MODE): ... this.  Remove V16HFmode.
	(VALID_AVX512F_SCALAR_MODE): Remove HImode and HFmode.
	(VALID_AVX512FP16_SCALAR_MODE): New.
	(VALID_AVX512F_REG_MODE): Add V32HFmode.
	(VALID_SSE2_REG_MODE): Add V8HFmode, V4HFmode and V2HFmode.
	(VALID_SSE2_REG_VHF_MODE): Remove.
	(VALID_INT_MODE_P): Add V2HFmode.
	* config/i386/i386.c (function_arg_advance_64):
	Remove explicit mention of V16HFmode and V32HFmode.
	(ix86_hard_regno_mode_ok): Remove explicit mention of XImode
	and V32HFmode, use VALID_AVX512F_REG_OR_XI_MODE instead.
	Use VALID_AVX512FP_SCALAR_MODE for TARGET_aVX512FP16.
	Use VALID_AVX256_REG_OR_OI_MODE instead of
	VALID_AVX256_REG_OR_OI_VHF_MODE and VALID_SSE2_REG_MODE instead
	of VALID_SSE2_REG_VHF_MODE.
	(ix86_set_reg_reg_cost): Remove usge of VALID_AVX512FP16_REG_MODE.
	(ix86_vector_mode_supported): Ditto.

gcc/testsuite/ChangeLog:

	PR target/103571
	* gcc.target/i386/pr102812.c (dg-final): Do not scan for movdqa.

ChangeLog:

	* config.sub: Fix typo.

	PR target/103709

gcc/c-family/ChangeLog:

	* c-pragma.c (handle_pragma_pop_options): Do not check
	global options modification when an error is seen in parsing
	of options (pragmas or attributes).

In g:01ad8c54 we started supporting target pragma changes
that are primarily caused by optimization option. The same can happen
in the opposite way and we need to check for changes both
in optimization_current_node and target_option_current_node.

	PR c++/103696

gcc/ChangeLog:

	* attribs.c (decl_attributes): Check if
	target_option_current_node is changed.

gcc/testsuite/ChangeLog:

	* g++.target/i386/pr103696.C: New test.

PR libfortran/101255

libgfortran/ChangeLog:

	* io/file_pos.c: Fix error code.

gcc/testsuite/ChangeLog:

	* gfortran.dg/iostat_5.f90: New file.

PR libfortran/98507

libgfortran/ChangeLog:

	* intrinsics/time_1.h: Prefer clock_gettime() over
	  gettimeofday().
	* intrinsics/date_and_time.c: Fix timezone wrapping.

gcc/testsuite/ChangeLog:

	* gfortran.dg/date_and_time_1.f90: New file.

gcc/ChangeLog:

	* doc/invoke.texi: Add missing dash.

While replacing the built-in machinery, we agreed to defer some necessary
refactoring of the overload processing.  This patch cleans it up considerably.

I've put in one FIXME for an additional level of cleanup that should be done
independently.  The various helper functions (resolve_VEC_*) can be simplified
if we move the argument processing in altivec_resolve_overloaded_builtin
earlier.  But this requires making nontrivial changes to those functions that
will need careful review.  Let's do that in a later patch.

2021-12-16  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-c.c (resolution): New enum.
	(resolve_vec_mul): New function.
	(resolve_vec_cmpne): Likewise.
	(resolve_vec_adde_sube): Likewise.
	(resolve_vec_addec_subec): Likewise.
	(resolve_vec_splats): Likewise.
	(resolve_vec_extract): Likewise.
	(resolve_vec_insert): Likewise.
	(resolve_vec_step): Likewise.
	(find_instance): Likewise.
	(altivec_resolve_overloaded_builtin): Many cleanups.  Call factored-out
	functions.  Move variable declarations closer to uses.  Add commentary.
	Remove unnecessary levels of braces.  Avoid use of gotos.  Change
	misleading variable names.  Use switches over if-else-if chains.

This patch is sorting issue with LS64 intrinsics tests failing with
AArch64_be targets.

gcc/ChangeLog:

	PR target/103729
	* config/aarch64/aarch64-simd.md (aarch64_movv8di): Allow big endian
	targets to move V8DI.

gcc/ChangeLog:

	PR driver/103644
	* gcc.c (check_offload_target_name): Add 'default' and 'disable'
	to the candidate list.

This reverts commit bf8cdd35.

Also add verbose argument support like analyze_brprob.py

contrib/ChangeLog:

	* analyze_brprob_spec.py: Add verbose argument.

My r11-2202 was trying to enforce [dcl.type.auto.deduct]/4, which says
"If the placeholder-type-specifier is of the form type-constraint[opt]
decltype(auto), T shall be the placeholder alone."  But this made us
reject 'constexpr decltype(auto)', which, after clarification from CWG,
should be valid.  [dcl.type.auto.deduct]/4 is supposed to be a syntactic
constraint, not semantic, so it's OK that the constexpr marks the object
as const.

As a consequence, checking TYPE_QUALS in do_auto_deduction is too late,
and we have a FIXME there anyway.  So in this patch I'm attempting to
detect 'const decltype(auto)' earlier.  If I'm going to use TYPE_QUALS,
it needs to happen before we mark the object as const due to constexpr,
that is, before grokdeclarator's

  /* A `constexpr' specifier used in an object declaration declares
     the object as `const'.  */
  if (constexpr_p && innermost_code != cdk_function)
    ...

Constrained decltype(auto) was a little problem, hence the TYPENAME
check.  But in a typename context you can't use decltype(auto) anyway,
I think.

	PR c++/102229

gcc/cp/ChangeLog:

	* decl.c (check_decltype_auto): New.
	(grokdeclarator): Call it.
	* pt.c (do_auto_deduction): Don't check decltype(auto) here.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp1y/decltype-auto5.C: New test.

For example, for the two (FAIL, XFAIL)
'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-test-1' cases:

    -FAIL: g++.dg/modules/xtreme-header-3_a.H -std=c++17 (internal compiler error)
    +FAIL: g++.dg/modules/xtreme-header-3_a.H -std=c++17 (internal compiler error: tree check: expected var_decl or function_decl or field_decl or type_decl or concept_decl or template_decl, have namespace_decl in get_merge_kind, at cp/module.cc:10072)

    -FAIL: gfortran.dg/gomp/clauses-1.f90   -O  (internal compiler error)
    +FAIL: gfortran.dg/gomp/clauses-1.f90   -O  (internal compiler error: Segmentation fault)

    -XFAIL: c-c++-common/goacc/kernels-decompose-ice-1.c (internal compiler error)
    +XFAIL: c-c++-common/goacc/kernels-decompose-ice-1.c (internal compiler error: in lower_omp_target, at omp-low.c:13147)

    -XFAIL: g++.dg/cpp1z/constexpr-lambda26.C  -std=c++17 (internal compiler error)
    +XFAIL: g++.dg/cpp1z/constexpr-lambda26.C  -std=c++17 (internal compiler error: in cxx_eval_constant_expression, at cp/constexpr.c:6954)

That allows for more easily spotting when during development you're trading one
ICE for another.

	gcc/testsuite/
	* lib/fortran-torture.exp (fortran-torture-compile)
	(fortran-torture-execute): Be more informative for ICEs.
	* lib/gcc-defs.exp (${tool}_check_compile): Likewise.
	* lib/gcc-dg.exp (gcc-dg-test-1): Likewise.
	* lib/go-torture.exp (go-torture-compile, go-torture-execute):
	Likewise.

Sync with binutils for building binutils with LTO:

1dbde357be3 Add missing changes to Makefile.tpl
af019bfde9b Support the PGO build for binutils+gdb

Add the --enable-pgo-build[=lto] configure option.  When binutils+gdb
is not built together with GCC, --enable-pgo-build enables the PGO build:

1. First build with -fprofile-generate.
2. Use "make maybe-check-*" to generate profiling data and pass -i to make
to ignore errors when generating profiling data.
3. Use "make clean" to remove the previous build.
4. Rebuild with -fprofile-use.

With --enable-pgo-build=lto, -flto=jobserver -ffat-lto-objects are used
together with -fprofile-generate and -fprofile-use.  Add '+' to the command
line for recursive make to support -flto=jobserver -ffat-lto-objects.

NB: --enable-pgo-build=lto enables the PGO build with LTO while
--enable-lto enables LTO support in toolchain.

	BZ binutils/26766
	* Makefile.tpl (BUILD_CFLAGS): New.
	(CFLAGS): Append $(BUILD_CFLAGS).
	(CXXFLAGS): Likewise.
	(PGO_BUILD_GEN_FLAGS_TO_PASS): New.
	(PGO_BUILD_TRAINING_CFLAGS): Likewise.
	(PGO_BUILD_TRAINING_CXXFLAGS): Likewise.
	(PGO_BUILD_TRAINING_FLAGS_TO_PASS): Likewise.
	(PGO_BUILD_TRAINING_MFLAGS): Likewise.
	(PGO_BUILD_USE_FLAGS_TO_PASS): Likewise.
	(PGO-TRAINING-TARGETS): Likewise.
	(PGO_BUILD_TRAINING): Likewise.
	(all): Add '+' to the command line for recursive make.  Support
	the PGO build.
	* configure.ac: Add --enable-pgo-build[=lto].
	AC_SUBST PGO_BUILD_GEN_CFLAGS, PGO_BUILD_USE_CFLAGS and
	PGO_BUILD_LTO_CFLAGS.  Enable the PGO build in Makefile.
	* Makefile.in: Regenerated.
	* configure: Likewise.

Sync with binutils for building binutils with LTO:

50ad1254d50 GCC: Pass --plugin to AR and RANLIB

Detect GCC LTO plugin.  Pass --plugin to AR and RANLIB to support LTO
build.

ChangeLog:

	* Makefile.tpl (AR): Add @AR_PLUGIN_OPTION@
	(RANLIB): Add @RANLIB_PLUGIN_OPTION@.
	* configure.ac: Include config/gcc-plugin.m4.
	AC_SUBST AR_PLUGIN_OPTION and RANLIB_PLUGIN_OPTION.
	* libtool.m4 (_LT_CMD_OLD_ARCHIVE): Pass --plugin to AR and
	RANLIB if possible.
	* Makefile.in: Regenerated.
	* configure: Likewise.

config/

	* gcc-plugin.m4 (GCC_PLUGIN_OPTION): New.

libiberty/

	* Makefile.in (AR): Add @AR_PLUGIN_OPTION@
	(RANLIB): Add @RANLIB_PLUGIN_OPTION@.
	(configure_deps): Depend on ../config/gcc-plugin.m4.
	* configure.ac: AC_SUBST AR_PLUGIN_OPTION and
	RANLIB_PLUGIN_OPTION.
	* aclocal.m4: Regenerated.
	* configure: Likewise.

zlib/

	* configure: Regenerated.

Prefer to overload __to_address to partially specialize std::pointer_traits because
std::pointer_traits would be mostly useless. Moreover partial specialization of
pointer_traits<__normal_iterator<P, C>> fails to rebind C, so you get incorrect types
like __normal_iterator<long*, vector<int>>. In the case of __gnu_debug::_Safe_iterator
the to_pointer method is impossible to implement correctly because we are missing
the parent container to associate the iterator to.

libstdc++-v3/ChangeLog:

	* include/bits/stl_iterator.h
	(std::pointer_traits<__gnu_cxx::__normal_iterator<>>): Remove.
	(std::__to_address(const __gnu_cxx::__normal_iterator<>&)): New for C++11 to C++17.
	* include/debug/safe_iterator.h
	(std::__to_address(const __gnu_debug::_Safe_iterator<__gnu_cxx::__normal_iterator<>,
	_Sequence>&)): New for C++11 to C++17.
	* testsuite/24_iterators/normal_iterator/to_address.cc: Add check on std::vector::iterator
	to validate both __gnu_cxx::__normal_iterator<> __to_address overload in normal mode and
	__gnu_debug::_Safe_iterator in _GLIBCXX_DEBUG mode.

D front-end changes:

    - Import dmd v2.098.1-beta.1.
    - Default extern(C++) compatibility to C++17.

Druntime changes:

    - Import druntime v2.098.1-beta.1.
    - Fix definition of stat_t on MIPS64 (PR103604)

Phobos changes:

    - Import phobos v2.098.1-beta.1.

gcc/d/ChangeLog:

	* d-lang.cc (d_init_options): Set default -fextern-std= to C++17.
	* dmd/MERGE: Merge upstream dmd 93108bb9e.
	* gdc.texi (Runtime Options): Document the default for -fextern-std=.

libphobos/ChangeLog:

	PR d/103604
	* configure: Regenerate.
	* configure.ac (libtool_VERSION): Update to 3:0:0.
	* libdruntime/MERGE: Merge upstream druntime 6364e010.
	* src/MERGE: Merge upstream phobos 575b67a9b.
	* testsuite/libphobos.traits/all_satisfy.d: New test.
	* testsuite/libphobos.traits/traits.exp: New test.

gcc/testsuite/ChangeLog:
	PR tree-optimization/78969
	* gcc.dg/tree-ssa/builtin-snprintf-warn-6.c: New test.

We now use a C++ compiler so that we need to process
CXXFLAGS as well as CFLAGS in the gcc-plugin config
fragment.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>

config/ChangeLog:

	* gcc-plugin.m4: Save and process CXXFLAGS.

gcc/ChangeLog:

	* configure: Regenerate.

libcc1/ChangeLog:

	* configure: Regenerate.

Add new target macros TARGET_SM75 and TARGET_SM80.  Add support for
__builtin_tanhf, HFmode exp2/tanh and also for HFmode min/max, controlled by
TARGET_SM75 and TARGET_SM80 respectively.

The following has been tested on nvptx-none, hosted on x86_64-pc-linux-gnu
with a "make" and "make -k check" with no new failures.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (ptx_isa): PTX_ISA_SM75 and PTX_ISA_SM80
	ISA levels.
	* config/nvptx/nvptx.opt: Add sm_75 and sm_80 to -misa.
	* config/nvptx/nvptx.h (TARGET_SM75, TARGET_SM80):
	New helper macros to conditionalize functionality on target ISA.
	* config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
	support for the new ISA levels.
	* config/nvptx/nvptx.c (nvptx_file_start): Add support for TARGET_SM75
	and TARGET_SM80.
	* config/nvptx/nvptx.md (define_c_enum "unspec"): New UNSPEC_TANH.
	(define_mode_iterator HSFM): New iterator for HFmode and SFmode.
	(exp2hf2): New define_insn controlled by TARGET_SM75.
	(tanh<mode>2): New define_insn controlled by TARGET_SM75.
	(sminhf3, smaxhf3): New define_isnns controlled by TARGET_SM80.

gcc/testsuite/ChangeLog:

	* gcc.target/nvptx/float16-2.c: New test case.
	* gcc.target/nvptx/tanh-1.c: New test case.

Add support for ptx isa version 7.0, required for the addition of -misa=sm_75
and -misa=sm_80.

Tested by setting the default ptx isa version to 7.0, and doing a build and
libgomp test run.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_7_0.
	* config/nvptx/nvptx.c (nvptx_file_start): Handle TARGET_PTX_7_0.
	* config/nvptx/nvptx.h (TARGET_PTX_7_0): New macro.
	* config/nvptx/nvptx.opt (ptx_version): Add 7.0.

In this PR we were wrongly classifying a pair of 8-byte vectors
as a 16-byte “short vector” (in the AAPCS64 sense).  As the
comment in the patch says, this stems from an old condition
in aarch64_short_vector_p that is too loose, but that would
be difficult to tighten now.

We can still do the right thing for the newly-added modes though,
since there are no backwards compatibility concerns there.

Co-authored-by: Tamar Christina <tamar.christina@arm.com>

gcc/
	PR target/103094
	* config/aarch64/aarch64.c (aarch64_short_vector_p): Return false
	for structure modes, rather than ignoring the type in that case.

gcc/testsuite/
	PR target/103094
	* gcc.target/aarch64/pr103094.c: New test.

	PR c++/103713

gcc/cp/ChangeLog:

	* tree.c (maybe_warn_parm_abi): Fix warning word splitting.

This and the report in PR103632 are caused by a bug in REE where it generates
incorrect code.

It's trying to eliminate the following zero extension

(insn 54 90 102 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))

by folding it in the definition of `v8`:

(insn 2 5 104 2 (set (reg/v:V4HI 40 v8)
        (reg:V4HI 32 v0 [156]))
     (nil))

which is fine, except that `v8` is also used by the extracts, e.g.:

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8)
                (parallel [
                        (const_int 3)
                    ]))))
     (nil))

REE replaces insn 2 by folding insn 54 and placing it at the definition site of
insn 2, so before insn 11.

Trying to eliminate extension:
(insn 54 90 102 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))
Tentatively merged extension with definition (copy needed):
(insn 2 5 104 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg:V4HI 32 v0)))
     (nil))

to produce

(insn 2 5 110 2 (set (reg:V4SI 33 v1)
        (zero_extend:V4SI (reg:V4HI 32 v0)))
     (nil))
(insn 110 2 104 2 (set (reg:V4SI 40 v8)
        (reg:V4SI 33 v1))
     (nil))

The new insn 2 using v0 directly is correct, but the insn 110 it creates is
wrong, `v8` should still be V4HI.

or it also needs to eliminate the zero extension from the extracts, so instead
of

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8)
                (parallel [
                        (const_int 3)
                    ]))))
     (nil))

it should be

(insn 11 10 12 2 (set (reg:SI 1 x1)
        (vec_select:SI (reg/v:V4SI 40 v8)
                (parallel [
                        (const_int 3)
                    ])))
     (nil))

without doing so the indices have been remapped in the extension and so we
extract the wrong elements

At any other optimization level but -Os ree seems to abort so this doesn't
trigger:

Trying to eliminate extension:
(insn 54 90 101 2 (set (reg:V4SI 32 v0)
        (zero_extend:V4SI (reg/v:V4HI 40 v8)))
     (nil))
Elimination opportunities = 2 realized = 0

purely due to the ordering of instructions. REE doesn't check uses of `v8`
because it assumes that with a zero extended value, you still have access to the
lower bits by using the the bottom part of the register.

This is true for scalar but not for vector.  This would have been fine as well
if REE had eliminated the zero_extend on insn 11 and the rest but it doesn't do
so since REE can only handle cases where the SRC value are REG_P.

It does try to do this in add_removable_extension:

 1160      /* For vector mode extensions, ensure that all uses of the
 1161         XEXP (src, 0) register are in insn or debug insns, as unlike
 1162         integral extensions lowpart subreg of the sign/zero extended
 1163         register are not equal to the original register, so we have
 1164         to change all uses or none and the current code isn't able
 1165         to change them all at once in one transaction.  */

However this code doesn't trigger for the example because REE doesn't check the
uses if the defining instruction doesn't feed into another extension..

Which is bogus. For vectors it should always check all usages.

r12-2288-g8695bf78dad1a42636775843ca832a2f4dba4da3 simply exposed this as it now
lowers VEC_SELECT 0 into the RTL canonical form subreg 0 which causes REE to run
more often.

gcc/ChangeLog:

	PR rtl-optimization/103350
	* ree.c (add_removable_extension): Don't stop at first definition but
	inspect all.

gcc/testsuite/ChangeLog:

	PR rtl-optimization/103350
	* gcc.target/aarch64/pr103350-1.c: New test.
	* gcc.target/aarch64/pr103350-2.c: New test.

This test fails:
+FAIL: g++.dg/cpp23/auto-fncast11.C  -std=c++2b  (test for errors, line 19)
+FAIL: g++.dg/cpp23/auto-fncast11.C  -std=c++2b (test for excess errors)
because the regex in dg-error was missing an indefinite article.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/103408
	* g++.dg/cpp23/auto-fncast11.C: Fix expected diagnostic wording.

On Tue, Dec 14, 2021 at 10:32:21AM -0700, Jeff Law wrote:
> I think the attached testcase should trigger on c6x with -mbig-endian -O2 -g

Thanks.  Finally I see what's going on.  c6x doesn't really need the CFA
with span > 1 (and I bet neither does armbe), the only reason why
dwf_cfa_reg is called is that the code in 13 cases just tries to compare
the CFA against dwf_cfa_reg (some_reg).  And that dwf_cfa_reg on some reg
that usually isn't a CFA reg results in targetm.dwarf_register_span hook
call, which on targets like c6x or armeb and others for some registers
creates a PARALLEL with various REGs in it, then the loop with the assertion
and finally operator== which just notes that the reg is different and fails.

This seems compile time memory and time inefficient.

The following so far untested patch instead adds an extra operator== and !=
for comparison of cfa_reg with rtx, which has the most common case where it
is a different register number done early without actually invoking
dwf_cfa_reg.  This means the assertion in dwf_cfa_reg can stay as is (at
least until some big endian target needs to have hard frame pointer or stack
pointer with span > 1 as well).
I've removed a different assertion there because it is redundant - dwf_regno
already has exactly that assertion in it too.

And I've included those 2 tweaks to avoid creating a REG in GC memory when
we can use {stack,hard_frame}_pointer_rtx which is already initialized to
the same REG we need by init_emit_regs.

On Tue, Dec 14, 2021 at 03:05:37PM -0700, Jeff Law wrote:
> So if someone is unfamiliar with the underlying issues here and needs to
> twiddle dwarf2cfi, how are they supposed to know if they should compare
> directly or use dwf_cfa_reg?

Comparison without dwf_cfa_reg should be used whenever possible, because
for registers which are never CFA related that won't call
targetm.dwarf_register_span uselessly.

The only comparisons with dwf_cfa_reg I've kept are the:
            regno = dwf_cfa_reg (XEXP (XEXP (dest, 0), 0));

            if (cur_cfa->reg == regno)
              offset -= cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == regno)
              offset -= cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == regno);
                offset -= cur_trace->cfa_temp.offset;
              }
and
            struct cfa_reg regno = dwf_cfa_reg (XEXP (dest, 0));

            if (cur_cfa->reg == regno)
              offset = -cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == regno)
              offset = -cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == regno);
                offset = -cur_trace->cfa_temp.offset;
              }
and there are 2 reasons for it:
1) there is an assertion, which guarantees it must compare equal to one of
those 3 cfa related struct cfa_reg structs, so it must be some CFA related
register (so, right now, targetm.dwarf_register_span shouldn't return
non-NULL in those on anything but gcn)
2) it is compared 3 times in a row, so for the GCN case doing
            if (cur_cfa->reg == XEXP (XEXP (dest, 0), 0))
              offset -= cur_cfa->offset;
            else if (cur_trace->cfa_store.reg == XEXP (XEXP (dest, 0), 0))
              offset -= cur_trace->cfa_store.offset;
            else
              {
                gcc_assert (cur_trace->cfa_temp.reg == XEXP (XEXP (dest, 0), 0));
                offset -= cur_trace->cfa_temp.offset;
              }
could actually create more GC allocated garbage than the way it is written
now.  But doing it that way would work fine.

I think for most of the comparisons even comparing with dwf_cfa_reg would
work but be less compile time/memory efficient (e.g. those assertions that
it is equal to some CFA related cfa_reg or in any spots where only the CFA
related regs may appear in the frame related patterns).

I'm aware just of a single spot where comparison with dwf_cfa_reg doesn't
work (when the assert is in dwf_cfa_reg), that is the spot that was ICEing
on your testcase, where we save arbitrary call saved register:
      if (REG_P (src)
          && REGNO (src) != STACK_POINTER_REGNUM
          && REGNO (src) != HARD_FRAME_POINTER_REGNUM
          && cur_cfa->reg == src)

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR debug/103619
	* dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert.
	(operator==, operator!=): New overloaded operators.
	(dwarf2out_frame_debug_adjust_cfa, dwarf2out_frame_debug_cfa_offset,
	dwarf2out_frame_debug_expr): Compare vars with cfa_reg type directly
	with REG rtxes rather than with dwf_cfa_reg results on those REGs.
	(create_cie_data): Use stack_pointer_rtx instead of
	gen_rtx_REG (Pmode, STACK_POINTER_REGNUM).
	(execute_dwarf2_frame): Use hard_frame_pointer_rtx instead of
	gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM).

	PR target/103661

gcc/ChangeLog:

	* config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0
	as API expects that non-zero values are returned (do that
	it mask == 31).
	For "avx512vbmi2" argument, we return now 1 << 31, which is a
	negative integer value.

On OMP_CLAUSEs we reuse TREE_TYPE as CP_OMP_CLAUSE_INFO in the C++ FE.
This confuses the hashing code that operand_equal_p does when checking.
There is really no reason to compare OMP_CLAUSEs against expressions
like captured this, they will never compare equal.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/103704
	* semantics.c (finish_omp_target_clauses_r): For OMP_CLAUSEs
	just walk subtrees.

	* g++.dg/gomp/pr103704.C: New test.

This patch uses the same not completely correct case insensitive comparisons
as used elsewhere in the same header.  Proper comparisons that would handle
even multi-byte characters would be harder, but I don't see them implemented
in __ctype's methods.

2021-12-15  Jakub Jelinek  <jakub@redhat.com>

	PR libstdc++/71557
	* include/bits/locale_facets_nonio.tcc (_M_extract_via_format):
	Compare characters other than format specifiers and whitespace
	case insensitively.
	(_M_extract_name): Compare characters case insensitively.
	* testsuite/22_locale/time_get/get/char/71557.cc: New test.
	* testsuite/22_locale/time_get/get/wchar_t/71557.cc: New test.

Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand.

gcc/ChangeLog:

	PR target/101796
	* config/i386/predicates.md (const_vector_operand):
	Add new predicate.
	* config/i386/sse.md(<insn><mode>3<mask_name>):
	Add new define_split below.

gcc/testsuite/ChangeLog:

	PR target/101796
	* gcc.target/i386/pr101796-1.c: New test.

This patch implements XXSPLTIDP support for SF, and DF scalar constants.
The previous patch added support for vector constants.  This patch adds
the support for SFmode and DFmode scalar constants.

I added 2 new tests to test loading up SF and DF scalar constants.

2021-12-15  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
	(UNSPEC_XXSPLTIW_CONST): New unspec.
	(movsf_hardfloat): Add support for generating XXSPLTIDP.
	(mov<mode>_hardfloat32): Likewise.
	(mov<mode>_hardfloat64): Likewise.
	(xxspltidp_<mode>_internal): New insns.
	(xxspltiw_<mode>_internal): New insns.
	(splitters for SF/DFmode): Add new splitters for XXSPLTIDP.

gcc/testsuite/

	* gcc.target/powerpc/vec-splat-constant-df.c: New test.
	* gcc.target/powerpc/vec-splat-constant-sf.c: New test.

This patch implements XXSPLTIDP support for all vector constants.  The
XXSPLTIDP instruction is given a 32-bit immediate that is converted to a vector
of two DFmode constants.  The immediate is in SFmode format, so only constants
that fit as SFmode values can be loaded with XXSPLTIDP.

The constraint (eP) added in the previous patch for XXSPLTIW is also used
for XXSPLTIDP.

DImode scalar constants are not handled.  This is due to the majority of DImode
constants will be in the GPR registers.  With vector registers, you have the
problem that XXSPLTIDP splats the double word into both elements of the
vector.  However, if TImode is loaded with an integer constant, it wants a full
128-bit constant.

SFmode and DFmode scalar constants are not handled in this patch.  The
support for for those constants will be in the next patch.

I have added a temporary switch (-msplat-float-constant) to control whether or
not the XXSPLTIDP instruction is generated.

I added 2 new tests to test loading up V2DI and V2DF vector constants.

2021-12-14  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating XXSPLTIDP.
	(vsx_prefixed_constant): Likewise.
	(easy_vector_constant): Likewise.
	* config/rs6000/rs6000-protos.h (constant_generates_xxspltidp):
	New declaration.
	* config/rs6000/rs6000.c (output_vec_const_move): Add support for
	generating XXSPLTIDP.
	(prefixed_xxsplti_p): Likewise.
	(constant_generates_xxspltidp): New function.
	* config/rs6000/rs6000.opt (-msplat-float-constant): New debug option.

gcc/testsuite/

	* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
	regex for power10.
	* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.

This patch adds support to automatically generate the ISA 3.1 XXSPLTIW
instruction for V8HImode, V4SImode, and V4SFmode vectors.  It does this by
adding support for vector constants that can be used, and adding a
VEC_DUPLICATE pattern to generate the actual XXSPLTIW instruction.

Add the eP constraint to recognize constants that can be loaded into
vector registers with a single prefixed instruction such as xxspltiw and
xxspltidp.

I added 4 new tests to test loading up V16QI, V8HI, V4SI, and V4SF vector
constants.

2021-12-14  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/constraints.md (eP): Update comment.
	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating XXSPLTIW.
	(vsx_prefixed_constant): New predicate.
	(easy_vector_constant): Add support for
	generating XXSPLTIW.
	* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
	declaration.
	(constant_generates_xxspltiw): Likewise.
	* config/rs6000/rs6000.c (xxspltib_constant_p): Generate XXSPLTIW
	if possible instead of XXSPLTIB and sign extending the constant.
	(output_vec_const_move): Add support for XXSPLTIW.
	(prefixed_xxsplti_p): New function.
	(constant_generates_xxspltiw): New function.
	* config/rs6000/rs6000.md (prefixed attribute): Add support to
	mark XXSPLTI* instructions as being prefixed.
	* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
	switch.
	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
	generating XXSPLTIW or XXSPLTIDP.
	(vsx_mov<mode>_32bit): Likewise.
	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
	eP constraint.

gcc/testsuite/

	* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
	* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
	* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.

This patch adds support to generate the LXVKQ instruction to load specific
IEEE-128 floating point constants.

Compared to the last time I submitted this patch, I modified it so that it
uses the bit pattern of the vector to see if it can generate the LXVKQ
instruction.  This means on a little endian Power<xxx> system, the
following code will generate a LXVKQ 34,16 instruction:

    vector long long foo (void)
    {
      return (vector long long) { 0x0000000000000000, 0x8000000000000000 };
    }

because that vector pattern is the same bit pattern as -0.0F128.

2021-12-14  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/constraints.md (eQ): New constraint.
	* config/rs6000/predicates.md (easy_fp_constant): Add support for
	generating the LXVKQ instruction.
	(easy_vector_constant_ieee128): New predicate.
	(easy_vector_constant): Add support for generating the LXVKQ
	instruction.
	* config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New
	declaration.
	* config/rs6000/rs6000.c (output_vec_const_move): Add support for
	generating LXVKQ.
	(constant_generates_lxvkq): New function.
	* config/rs6000/rs6000.opt (-mieee128-constant): New debug
	option.
	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
	generating LXVKQ.
	(vsx_mov<mode>_32bit): Likewise.
	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
	eQ constraint.

gcc/testsuite/

	* gcc.target/powerpc/float128-constant.c: New test.

This patch provides the data structure and function to convert a
CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a constant) to
an array of bytes, half-words, words, and  double words that can be loaded
into a 128-bit vector register.

The next patches will use this data structure to generate code that
generates load of the vector/floating point registers using the XXSPLTIDP,
XXSPLTIW, and LXVKQ instructions that were added in power10.

2021-12-15  Michael Meissner  <meissner@the-meissners.org>

gcc/

	* config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro.
	(VECTOR_128BIT_BYTES): Likewise.
	(VECTOR_128BIT_HALF_WORDS): Likewise.
	(VECTOR_128BIT_WORDS): Likewise.
	(VECTOR_128BIT_DOUBLE_WORDS): Likewise.
	(vec_const_128bit_type): New structure type.
	(vec_const_128bit_to_bytes): New declaration.
	* config/rs6000/rs6000.c (constant_int_to_128bit_vector): New
	helper function.
	(constant_fp_to_128bit_vector): New helper function.
	(vec_const_128bit_to_bytes): New function.

The conversion of a MEM address to ptr_mode in
try_store_by_multiple_pieces was misguided: copy_addr_to_reg expects
Pmode for addresses.


for  gcc/ChangeLog

	PR target/100518
	* builtins.c (try_store_by_multiple_pieces): Drop address
	conversion to ptr_mode.

for  gcc/testsuite/ChangeLog

	PR target/100518
	* gcc.target/aarch64/pr100518.c: New.

The testcase confuses the code that detects min and max len for the
memset, so max_len ends up less than min_len.  That shouldn't be
possible, but the testcase requires us to handle this case.

The store-by-mult-pieces algorithm actually relies on min and max
lengths, so if we find them to be inconsistent, the best we can do is
punting.


for  gcc/ChangeLog

	PR middle-end/100843
	* builtins.c (try_store_by_multiple_pieces): Fail if min_len
	is greater than max_len.

for  gcc/testsuite/ChangeLog

	PR middle-end/100843
	* gcc.dg/pr100843.c: New.