[PATCH] H8/300, libgcc: PR target/114222 For HImode call internal ffs() implementation instead of an external one

When INT_TYPE_SIZE < BITS_PER_WORD gcc emits a call to an external ffs()
implementation instead of a call to "__builtin_ffs()" – see function
init_optabs() in <SRCROOT>/gcc/optabs-libfuncs.cc. External ffs()
(which is usually the one from newlib) in turn calls __builtin_ffs()
what causes infinite recursion and stack overflow. This patch overrides
default gcc bahaviour for H8/300H (and newer) and provides a generic
ffs() implementation for HImode.

	PR target/114222
gcc/ChangeLog:

	* config/h8300/h8300.cc (h8300_init_libfuncs): For HImode override
	calls to external ffs() (from newlib) with calls to __ffshi2() from
	libgcc. The implementation of ffs() in newlib calls __builtin_ffs()
	what causes infinite recursion and finally a stack overflow.

libgcc/ChangeLog:

	* config/h8300/t-h8300: Add __ffshi2().
	* config/h8300/ffshi2.c: New file.

When gcc is built for x86_64-linux-musl target, stack unwinding from
within signal handler stops at the innermost signal frame.  The reason
for this behaviro is that the signal trampoline is not accompanied with
appropiate CFI directives, and the fallback path in libgcc to recognize
it by the code sequence is only enabled for glibc except 2.0.  The
latter is motivated by the lack of sys/ucontext.h in that glibc version.

Given that all relevant libc-s ship sys/ucontext.h for over a decade,
and that other arches aren't shy of unconditionally using it, follow
suit and remove the preprocessor condition, too.

libgcc/ChangeLog:

	* config/i386/linux-unwind.h: Remove preprocessor
	condition to enable fallback path for all libc-s.

Signed-off-by: Roman Kagan <rkagan@amazon.de>

Due to the presence of R_LARCH_B26 in
/usr/lib/gcc/loongarch64-linux-gnu/14/crtbeginS.o, its addressing
range is [PC-128MiB, PC+128MiB-4]. This means that when the code
segment size exceeds 128MB, linking with lld will definitely fail
(ld will not fail because the order of the two is different).

The linking order:
  lld: crtbeginS.o + .text + .plt
  ld : .plt + crtbeginS.o + .text

To solve this issue, add '-mcmodel=extreme' when compiling crtbeginS.o.

	PR target/118844

libgcc/ChangeLog:

	* config/loongarch/t-crtstuff: Add '-mcmodel=extreme'
	to CRTSTUFF_T_CFLAGS_S.

As discussed from RISC-V C-API PR #101 [1], As discussed in #96, current
interface is insufficient to support some cases, like a vendor buying a
CPU IP from the upstream vendor but using their own mvendorid and custom
features from the upstream vendor. In this case, we might need to add
these extensions for each downstream vendor many times. Thus, making
__riscv_vendor_feature_bits guarded by mvendorid is not a good idea. So,
drop __riscv_vendor_feature_bits for now, and we should have time to
discuss a better solution.

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/101



Signed-off-by: Yangyu Chen <cyy@cyyself.name>

gcc/ChangeLog:

	* config/riscv/riscv-feature-bits.h (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop.
	(struct riscv_vendor_feature_bits): Drop.

libgcc/ChangeLog:

	* config/riscv/feature_bits.c (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop.
	(__init_riscv_features_bits_linux): Drop.

Add crtbeginT.o to extra_parts on FreeBSD. This ensures we use GCC's
crt objects for static linking. Otherwise it could mix crtbeginT.o
from the base system with libgcc's crtend.o, possibly leading to
segfaults.

libgcc:
	PR target/118685
	* config.host (*-*-freebsd*): Add crtbeginT.o to extra_parts.

Signed-off-by: Dimitry Andric <dimitry@andric.com>

2025-02-07  Peter Bergner  <bergner@linux.ibm.com>

libgcc/
	PR target/117674
	* config/rs6000/linux-unwind.h (ppc_backchain_fallback): Add cast to
	avoid comparison between pointer and integer warning.

This patch adds built-in functions __builtin_avr_strlen_flash,
__builtin_avr_strlen_flashx and __builtin_avr_strlen_memx.
Purpose is that higher-level functions can use __builtin_constant_p
on strlen without raising a diagnostic due to -Waddr-space-convert.

gcc/
	* config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX)
	(STRLEN_MEMX): New DEF_BUILTIN's.
	* config/avr/avr.cc (avr_ftype_strlen): New static function.
	(avr_builtin_supported_p): New built-ins are not for AVR_TINY.
	(avr_init_builtins) <strlen_flash_node, strlen_flashx_node,
	strlen_memx_node>: Provide new fntypes.
	(avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH]
	[AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if
	possible.
	* doc/extend.texi (AVR Built-in Functions): Document
	__builtin_avr_strlen_flash, __builtin_avr_strlen_flashx,
	__builtin_avr_strlen_memx.
libgcc/
	* config/avr/t-avr (LIB1ASMFUNCS): Add _strlen_memx.
	* config/avr/lib1funcs.S <L_strlen_memx, __strlen_memx>: Implement.

The arm-none-eabi port provides some alternative implementations of
__sync_synchronize for different implementations of the architecture.
These can be selected using one of -specs=sync-{none,dmb,cp15dmb}.specs.

These specs fragments fail, however, when LTO is used because they
unconditionally add a --defsym=__sync_synchronize=<implementation> to
the linker arguments and that fails if libgcc is not added to the list
of libraries.

Fix this by only adding the defsym if libgcc will be passed to the
linker.

libgcc/

	PR target/118642
	* config/arm/sync-none.specs (link): Only add the defsym if
	libgcc will be used.
	* config/arm/sync-dmb.specs: Likewise.
	* config/arm/sync-cp15dmb.specs: Likewise.

gcc/ChangeLog:
	* config/riscv/riscv.cc
	(riscv_file_end): Add .note.gnu.property.

libgcc/ChangeLog:
	* config/riscv/crti.S: Add lpad instructions.
	* config/riscv/crtn.S: Likewise.
	* config/riscv/save-restore.S: Likewise.
	* config/riscv/riscv-asm.h: Add GNU_PROPERTY for ZICFILP,
	ZICFISS.

Co-Developed-by: Jesse Huang <jesse.huang@sifive.com>

This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.

RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi



gcc/ChangeLog:
	* common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
	* config/riscv/predicates.md: New predicate x1x5_operand.
	* config/riscv/riscv.cc
	(riscv_expand_prologue): Insert shadow stack instructions.
	(riscv_expand_epilogue): Likewise.
	(riscv_for_each_saved_reg): Assign t0 or ra register for
	sspopchk instruction.
	(need_shadow_stack_push_pop_p): New function. Omit shadow
	stack operation on leaf function.
	* config/riscv/riscv.h
	(need_shadow_stack_push_pop_p): Define.
	* config/riscv/riscv.md: Add shadow stack patterns.
	(save_stack_nonlocal): Add shadow stack instructions for setjump.
	(restore_stack_nonlocal): Add shadow stack instructions for longjump.
	* config/riscv/riscv.opt (TARGET_ZICFISS): Define.

libgcc/ChangeLog:
	* config/riscv/linux-unwind.h: Include shadow-stack-unwind.h.
	* config/riscv/shadow-stack-unwind.h
	(_Unwind_Frames_Extra): Define.
	(_Unwind_Frames_Increment): Define.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/ssp-1.c: New test.
	* gcc.target/riscv/ssp-2.c: New test.

Co-Developed-by: Greg McGary <gkm@rivosinc.com&gt;,>
			Kito Cheng <kito.cheng@gmail.com>

Fix __extenddfxf2:

  * Remove bogus denorm handling block which would never execute --
    the converted exp value is always positive as EXCESSX > EXCESSD.

  * Compute the whole significand in dl instead of doing part of it in
    ldl.

    * Mask off exponent from dl.l.upper so the denorm shift test
      works.

    * Insert the hidden one bit into dl.l.upper as needed.

Fix __truncxfdf2 denorm handling. All that is required is to shift the
significand right by the correct amount; it already has all of the
necessary bits set including the explicit one. Compute the shift
amount, then perform the wide shift across both elements of the
significand.

Fix __fixxfsi:

  * The value  was off by a factor of two as the significand contains
    32 bits, not 31 so we need to shift by one more than the equivalent
    code in __fixdfsi.

  * Simplify the code having realized that the lower 32 bits of the
    significand can never appear in the results.

Return positive qNaN instead of negative. For floats, qNaN is 0x7fff_ffff. For
doubles, qNaN is 0x7fff_ffff_ffff_ffff.

Return correctly signed zero on float and double divide underflow. This means
that Ld$underflow now expects d7 to contain the sign bit, just like the other
return paths.

libgcc/
	* config/m68k/fpgnulib.c (extenddfxf2): Simplify code by removing code
	that should never execute.  Fix denorm shift test and insert hidden bit
	as needed.
	(__truncxfdf2): Properly compue and shift the significant right.
	* config/m68k/lb1sf68.S (__fixxfsi): Correct shift counts and simplify.
	(QUIET_NAN): Make it a positive quiet NaN and fix return values to inject
	sign properly.

In the OpenRISC build we get the following warning:

    ld: warning: __modsi3_s.o: missing .note.GNU-stack section implies executable stack
    ld: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

Fix this by adding a .note.GNU-stack to indicate the stack does not need to be
executable for the lib1funcs.

Note, this is also needed for the upcoming glibc 2.41.

libgcc/
	* config/or1k/lib1funcs.S: Add .note.GNU-stack section on linux.

2024 -> 2025

This patch adds __flashx as a new named address space that allocates
objects in .progmemx.data.  The handling is mostly the same or similar
to that of 24-bit space __memx, except that the asm routines are
simpler and more efficient.  Loads are emit inline when ELPMX or
LPMX is available.  The address space uses a 24-bit addresses even
on devices with a program memory size of 64 KiB or less.

	PR target/118001
gcc/
	* doc/extend.texi (AVR Named Address Spaces): Document __flashx.
	* config/avr/avr.h (ADDR_SPACE_FLASHX): New enum value.
	* config/avr/avr-protos.h (avr_out_fload, avr_mem_flashx_p)
	(avr_fload_libgcc_p, avr_load_libgcc_mem_p)
	(avr_load_libgcc_insn_p): New.
	* config/avr/avr.cc (avr_addrspace): Add ADDR_SPACE_FLASHX.
	(avr_decl_flashx_p, avr_mem_flashx_p, avr_fload_libgcc_p)
	(avr_load_libgcc_mem_p, avr_load_libgcc_insn_p, avr_out_fload):
	New functions.
	(avr_adjust_insn_length) [ADJUST_LEN_FLOAD]: Handle case.
	(avr_progmem_p) [avr_decl_flashx_p]: return 2.
	(avr_addr_space_legitimate_address_p) [ADDR_SPACE_FLASHX]:
	Has same behavior like ADDR_SPACE_MEMX.
	(avr_addr_space_convert): Use pointer sizes rather then ASes.
	(avr_addr_space_contains): New function.
	(avr_convert_to_type): Use it.
	(avr_emit_cpymemhi): Handle ADDR_SPACE_FLASHX.
	* config/avr/avr.md (adjust_len) <fload>: New attr value.
	(gen_load<mode>_libgcc): Renamed from load<mode>_libgcc.
	(xload8<mode>_A): Iterate over MOVMODE rather than over ALL1.
	(fxmov<mode>_A): New from xloadv<mode>_A.
	(xmov<mode>_8): New from xload<mode>_A.
	(fmov<mode>): New insns.
	(fxload<mode>_A): New from xload<mode>_A.
	(fxload_<mode>_libgcc): New from xload_<mode>_libgcc.
	(*fxload_<mode>_libgcc): New from *xload_<mode>_libgcc.
	(mov<mode>) [avr_mem_flashx_p]: Hande ADDR_SPACE_FLASHX.
	(cpymemx_<mode>): Make sure the address space is not lost
	when splitting.
	(*cpymemx_<mode>) [ADDR_SPACE_FLASHX]: Use __movmemf_<mode> for asm.
	(*ashlqi.1.zextpsi_split): New combine pattern.
	* config/avr/predicates.md (nox_general_operand): Don't match
	when avr_mem_flashx_p is true.
	* config/avr/avr-passes.cc (AVR_LdSt_Props):
	ADDR_SPACE_FLASHX has no post_inc.

gcc/testsuite/
	* gcc.target/avr/torture/addr-space-1.h [AVR_HAVE_ELPM]:
	Use a function to bump .progmemx.data to a high address.
	* gcc.target/avr/torture/addr-space-2.h: Same.
	* gcc.target/avr/torture/addr-space-1-fx.c: New test.
	* gcc.target/avr/torture/addr-space-2-fx.c: New test.

libgcc/
	* config/avr/t-avr (LIB1ASMFUNCS): Add _fload_1, _fload_2,
	_fload_3, _fload_4, _movmemf.
	* config/avr/lib1funcs.S (.branch_plus): New .macro.
	(__xload_1, __xload_2, __xload_3, __xload_4): When the address is
	located in flash, then forward to...
	(__fload_1, __fload_2, __fload_3, __fload_4): ...these new
	functions, respectively.
	(__movmemx_hi): When the address is located in flash, forward to...
	(__movmemf_hi): ...this new function.

Unlike crtoffload{begin,end}.o which just define some symbols at the start/end
of the various .gnu.offload* sections, crtoffloadtable.o contains
const void *const __OFFLOAD_TABLE__[]
  __attribute__ ((__visibility__ ("hidden"))) =
{
  &__offload_func_table, &__offload_funcs_end,
  &__offload_var_table, &__offload_vars_end,
  &__offload_ind_func_table, &__offload_ind_funcs_end,
};
The problem is that linking this into PIEs or shared libraries doesn't
work when it is compiled without -fpic/-fpie - __OFFLOAD_TABLE__ for non-PIC
code is put into .rodata section, but it really needs relocations, so for
PIC it should go into .data.rel.ro/.data.rel.ro.local.
As I think we don't want .data.rel.ro section in non-PIE binaries, this patch
follows the path of e.g. crtbegin.o vs. crtbeginS.o and adds crtoffloadtableS.o
next to crtoffloadtable.o, where crtoffloadtableS.o is compiled with -fpic.

2024-11-30  Jakub Jelinek  <jakub@redhat.com>

	PR libgomp/117851
gcc/
	* lto-wrapper.cc (find_crtoffloadtable): Add PIE_OR_SHARED argument,
	search for crtoffloadtableS.o rather than crtoffloadtable.o if
	true.
	(run_gcc): Add pie_or_shared variable.  If OPT_pie or OPT_shared or
	OPT_static_pie is seen, set pie_or_shared to true, if OPT_no_pie is
	seen, set pie_or_shared to false.  Pass it to find_crtoffloadtable.
libgcc/
	* configure.ac (extra_parts): Add crtoffloadtableS.o.
	* Makefile.in (crtoffloadtableS$(objext)): New goal.
	* configure: Regenerated.

Including the "arm_acle.h" header in aarch64-unwind.h requires
stdint.h to be present and it may not be available during the
first stage of cross-compilation of GCC.

When cross-building GCC for the aarch64-none-linux-gnu target
(on any supporting host) using the 3-stage bootstrap build
process when we build native compiler from source, libgcc fails
to compile due to missing header that has not been installed yet.

This could be worked around but it's better to fix the issue.

libgcc/ChangeLog:

	* config/aarch64/aarch64-unwind.h (_CHKFEAT_GCS): Add.

gcc/ChangeLog:
	* config/aarch64/arm_acle.h (_CHKFEAT_GCS): New.

libgcc/ChangeLog:

	* config/aarch64/aarch64-unwind.h (_Unwind_Frames_Extra): Update.
	(_Unwind_Frames_Increment): Update

Reviewed-by: Richard Sandiford <richard.sandiford@arm.com>

nios2 target support in GCC was deprecated in GCC 14 as the
architecture has been EOL'ed by the vendor.  This patch removes the
entire port for GCC 15

There are still references to "nios2" in libffi and libgo.  Since those
libraries are imported into the gcc sources from master copies maintained
by other projects, those will need to be addressed elsewhere.

ChangeLog:
	* MAINTAINERS: Remove references to nios2.
	* configure.ac: Likewise.
	* configure: Regenerated.

config/ChangeLog:
	* mt-nios2-elf: Deleted.

contrib/ChangeLog:
	* config-list.mk: Remove references to Nios II.

gcc/ChangeLog:
	* common/config/nios2/*: Delete entire directory.
	* config/nios2/*: Delete entire directory.
	* config.gcc: Remove references to nios2.
	* configure.ac: Likewise.
	* doc/extend.texi: Likewise.
	* doc/install.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/md.texi: Likewise.
	* regenerate-opt-urls.py: Likewise.
	* config.in: Regenerated.
	* configure: Regenerated.

gcc/testsuite/ChangeLog:
	* g++.target/nios2/*: Delete entire directory.
	* gcc.target/nios2/*: Delete entire directory.
	* g++.dg/cpp0x/constexpr-rom.C: Remove refences to nios2.
	* g++.old-deja/g++.jason/thunk3.C: Likewise.
	* gcc.c-torture/execute/20101011-1.c: Likewise.
	* gcc.c-torture/execute/pr47237.c: Likewise.
	* gcc.dg/20020312-2.c: Likewise.
	* gcc.dg/20021029-1.c: Likewise.
	* gcc.dg/debug/btf/btf-datasec-1.c: Likewise.
	* gcc.dg/ifcvt-4.c: Likewise.
	* gcc.dg/stack-usage-1.c: Likewise.
	* gcc.dg/struct-by-value-1.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
	* lib/target-supports.exp: Likewise.

libgcc/ChangeLog:
	* config/nios2/*: Delete entire directory.
	* config.host: Remove refences to nios2.
	* unwind-dw2-fde-dip.c: Likewise.

The patch bypasses hidden attribute warnings in MinGW until it is
implemented.

libgcc/ChangeLog:

	* config.host: Update.
	* config/aarch64/t-mingw: New.

While these haven't shown up in my tester (not configs I test) and I think
we're likely going to be deprecating the nds32 target. we might as well go
ahead and fix them.

I'm going to include this under the pr117628 umbrella.

	PR target/117628

libgcc/
	* config/arm/freebsd-atomic.c (bool): Remove unnecessary typedef.
	* config/arm/linux-atomic-64bit.c: Likewise.
	* config/arm/linux-atomic.c: Likewise.
	* config/nds32/linux-atomic.c: Likewise.
	* config/nios2/linux-atomic.c: Likewise.

csky fails to build libgcc after the c23 changes because it has a typedef for
bool.  AFAICT it's internal to the file, so removing the typedef isn't an ABI
change.

Similiarly for c6x which includes unwind-arm-common.inc.  I suspect most, if
not all of the arm-v7 and older targets are failing to build right now.

I've built and regression tested both csky-linux-gnu and c6x-elf with this
change.  OK for the trunk?

	PR target/117628
libgcc/
	* config/csky/linux-atomic.c (bool): Remove unnecessary typedef.
	* unwind-arm-common.inc (bool): Similarly.