This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-rol-ror-08.c: New test.
	* gcc.target/riscv/zbb-rol-ror-09.c: New test.

Co-authored-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

This C++23 paper fixes an issue in these views when adapting a certain
kind of non-forward range, and we treat it as a DR against C++20.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>

libstdc++-v3/ChangeLog:

	* include/bits/regex.h (regex_iterator::iterator_concept):
	Define for C++20 as per P2770R0.
	(regex_token_iterator::iterator_concept): Likewise.
	* include/std/ranges (__detail::__as_lvalue): Define.
	(join_view::_Iterator): Befriend join_view.
	(join_view::_Iterator::_M_satisfy): Use _M_get_outer
	instead of _M_outer.
	(join_view::_Iterator::_M_get_outer): Define.
	(join_view::_Iterator::_Iterator): Split constructor taking
	_Parent argument into two as per P2770R0.  Remove constraint on
	default constructor.
	(join_view::_Iterator::_M_outer): Make this data member present
	only when the underlying range is forward.
	(join_view::_Iterator::operator++): Use _M_get_outer instead of
	_M_outer.
	(join_view::_Iterator::operator--): Use __as_lvalue helper.
	(join_view::_Iterator::operator==): Adjust constraints as per
	P2770R0.
	(join_view::_Sentinel::__equal): Use _M_get_outer instead of
	_M_outer.
	(join_view::_M_outer): New data member when the underlying range
	is non-forward.
	(join_view::begin): Adjust definition as per P2770R0.
	(join_view::end): Likewise.
	(join_with_view::_M_outer_it): New data member when the
	underlying range is non-forward.
	(join_with_view::begin): Adjust definition as per P2770R0.
	(join_with_view::end): Likewise.
	(join_with_view::_Iterator::_M_outer_it): Make this data member
	present only when the underlying range is forward.
	(join_with_view::_Iterator::_M_get_outer): Define.
	(join_with_view::_Iterator::_Iterator): Split constructor
	taking _Parent argument into two as per P2770R0.  Remove
	constraint on default constructor.
	(join_with_view::_Iterator::_M_update_inner): Adjust definition
	as per P2770R0.
	(join_with_view::_Iterator::_M_get_inner): Likewise.
	(join_with_view::_Iterator::_M_satisfy): Adjust calls to
	_M_get_inner.  Use _M_get_outer instead of _M_outer_it.
	(join_with_view::_Iterator::operator==): Adjust constraints
	as per P2770R0.
	(join_with_view::_Sentinel::operator==): Use _M_get_outer
	instead of _M_outer_it.
	* testsuite/std/ranges/adaptors/p2770r0.cc: New test.

Using the CRTP idiom for this base class avoids bloating the size of a
pipeline when adding distinct empty range adaptor closure objects to it,
as detailed in section 4.1 of P2387R3.

But it means we can no longer define its operator| overloads as hidden
friends, since it'd mean each instantiation of _RangeAdaptorClosure
introduces its own distinct set of hidden friends.  So e.g. for the
outer | in

  x | (views::reverse | views::join)

ADL would find 6 distinct hidden operator| friends:

  two from _RangeAdaptorClosure<_Reverse>
  two from _RangeAdaptorClosure<_Join>
  two from _RangeAdaptorClosure<_Pipe<_Reverse, _Join>>

but we really only want to consider the last two.

We avoid this issue by instead defining the operator| overloads at
namespace scope alongside _RangeAdaptorClosure.  This should be fine
because the only types defined in this namespace are _RangeAdaptorClosure,
_RangeAdaptor, _Pipe and _Partial, so we don't have to worry about
unintentional ADL.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>

	PR libstdc++/108827

libstdc++-v3/ChangeLog:

	* include/std/ranges (__adaptor::_RangeAdaptorClosure):
	Convert into a CRTP class template.  Move hidden operator|
	friends into namespace scope and adjust their constraints.
	(__closure::__is_range_adaptor_closure_fn): Define.
	(__closure::__is_range_adaptor_closure): Define.
	(__adaptor::_Partial): Adjust use of _RangeAdaptorClosure.
	(__adaptor::_Pipe): Likewise.
	(views::_All): Likewise.
	(views::_Join): Likewise.
	(views::_Common): Likewise.
	(views::_Reverse): Likewise.
	(views::_Elements): Likewise.
	(views::_Adjacent): Likewise.
	(views::_AsRvalue): Likewise.
	(views::_Enumerate): Likewise.
	(views::_AsConst): Likewise.
	* testsuite/std/ranges/adaptors/all.cc: Reinstate assertion
	expecting that adding empty range adaptor closure objects to a
	pipeline doesn't increase the size of a pipeline.

[LRA]: When assigning stack slots to pseudos previously assigned to fp consider other spilled pseudos

The previous LRA patch can assign slot of conflicting pseudos to
pseudos spilled after prohibiting fp->sp elimination.  This patch
fixes this problem.

gcc/ChangeLog:

	* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Moving
	slots_num initialization from here ...
	(lra_spill): ... to here before the 1st call of
	assign_stack_slot_num_and_sort_pseudos.  Add the 2nd call after
	fp->sp elimination.

GCC emits pedwarns unconditionally when comparing pointers of
different types, for example:

  int xdp_context (struct xdp_md *xdp)
    {
        void *data = (void *)(long)xdp->data;
        __u32 *metadata = (void *)(long)xdp->data_meta;
        __u32 ret;

        if (metadata + 1 > data)
          return 0;
        return 1;
   }

  /home/jemarch/foo.c: In function ‘xdp_context’:
  /home/jemarch/foo.c:15:20: warning: comparison of distinct pointer types lacks a cast
         15 |   if (metadata + 1 > data)
                 |                    ^

LLVM supports an option -W[no-]compare-distinct-pointer-types that can
be used in order to enable or disable the emission of such warnings.
It is enabled by default.

This patch adds the same options to GCC.

Documentation and testsuite updated included.
Regtested in x86_64-linu-gnu.
No regressions observed.

gcc/ChangeLog:

	PR c/106537
	* doc/invoke.texi (Option Summary): Mention
	-Wcompare-distinct-pointer-types under `Warning Options'.
	(Warning Options): Document -Wcompare-distinct-pointer-types.

gcc/c-family/ChangeLog:

	PR c/106537
	* c.opt (Wcompare-distinct-pointer-types): New option.

gcc/c/ChangeLog:

	PR c/106537
	* c-typeck.cc (build_binary_op): Warning on comparing distinct
	pointer types only when -Wcompare-distinct-pointer-types.

gcc/testsuite/ChangeLog:

	PR c/106537
	* gcc.c-torture/compile/pr106537-1.c: New test.
	* gcc.c-torture/compile/pr106537-2.c: Likewise.
	* gcc.c-torture/compile/pr106537-3.c: Likewise.

fr30 is the only target defining GO_IF_LEGITIMATE_ADDRESS right now, in
which case the `code_helper ch` argument to memory_address_addr_space_p()
is unused and emits a new warning.

gcc/ChangeLog:
	* recog.cc (memory_address_addr_space_p): Mark possibly unused
	argument as unused.

"#error Feature macro not defined" is required to test the existence of an
extension through the preprocessor.  However, multiple occurrence of the
exact same error message will confuse the developer once an error is
encountered.

This commit replaces such error messages to
"#error Feature macro for `EXT' not defined" to make which
macro is missing.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zvkn.c: Deduplicate #error messages.
	* gcc.target/riscv/zvkn-1.c: Ditto.
	* gcc.target/riscv/zvknc.c: Ditto.
	* gcc.target/riscv/zvknc-1.c: Ditto.
	* gcc.target/riscv/zvknc-2.c: Ditto.
	* gcc.target/riscv/zvkng.c: Ditto.
	* gcc.target/riscv/zvkng-1.c: Ditto.
	* gcc.target/riscv/zvkng-2.c: Ditto.
	* gcc.target/riscv/zvks.c: Ditto.
	* gcc.target/riscv/zvks-1.c: Ditto.
	* gcc.target/riscv/zvksc.c: Ditto.
	* gcc.target/riscv/zvksc-1.c: Ditto.
	* gcc.target/riscv/zvksc-2.c: Ditto.
	* gcc.target/riscv/zvksg.c: Ditto.
	* gcc.target/riscv/zvksg-1.c: Ditto.
	* gcc.target/riscv/zvksg-2.c: Ditto.

The following guards the bit test merging code in if-combine against
the appearance of SSA names used in abnormal PHIs.

	PR tree-optimization/111039
	* tree-ssa-ifcombine.cc (ifcombine_ifandif): Check for
	SSA_NAME_OCCURS_IN_ABNORMAL_PHI.

	* gcc.dg/pr111039.c: New testcase.

The documentation requires that numa_available() is called and only
when successful, other libnuma function may be called. Internally,
it does a syscall to get_mempolicy with flag=0 (which would return
the default policy if mode were not NULL). If this returns -1 (and
not 0) and errno == ENOSYS, the Linux kernel does not have the
get_mempolicy syscall function; if so, numa_available() returns -1
(otherwise: 0).

libgomp/

	PR libgomp/111024
	* allocator.c (gomp_init_libnuma): Call numa_available; if
	not available or not returning 0, disable libnuma usage.

This patch fixes up the code examples in the RTL-SSA documentation (the
sections on making insn changes) to reflect the current API.

The main issues are as follows:
 - rtl_ssa::recog takes an obstack_watermark & as the first parameter.
   Presumably this is intended to be the change attempt, so I've updated
   the examples to pass this through.
 - The variants of recog and restrict_movement that take an ignore
   predicate have been renamed with an _ignoring suffix, so I've
   updated callers to use those names.
 - A couple of minor "obvious" fixes to add a missing address-of
   operator and correct a variable name.

gcc/ChangeLog:

	* doc/rtl.texi: Fix up sample code for RTL-SSA insn changes.

This patch fixs XPASS slp testcases on trunk by
making the conditions for xfail stricter.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Fix.
	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto.

The kernel selftests and other BPF programs make extensive use of the
`naked' function attribute with bodies written using basic inline
assembly.  This patch adds support for the attribute to
bpf-unkonwn-none, makes it to inhibit warnings due to lack of explicit
`return' statement, and updates documentation and testsuite
accordingly.

Tested in x86_64-linux-gnu host and bpf-unknown-none target.

gcc/ChangeLog

	PR target/111046
	* config/bpf/bpf.cc (bpf_attribute_table): Add entry for the
	`naked' function attribute.
	(bpf_warn_func_return): New function.
	(TARGET_WARN_FUNC_RETURN): Define.
	(bpf_expand_prologue): Add preventive comment.
	(bpf_expand_epilogue): Likewise.
	* doc/extend.texi (BPF Function Attributes): Document the `naked'
	function attribute.

gcc/testsuite/ChangeLog

	* gcc.target/bpf/naked-1.c: New test.

std::format was treating {:f} and {:F} identically on the basis that for
the fixed 1.234567 format there are no alphabetical characters that need
to be in uppercase. But that's wrong for infinities and NaNs, which
should be formatted as "INF" and "NAN" for {:F}.

libstdc++-v3/ChangeLog:

	* include/std/format (__format::_Pres_type): Add _Pres_F.
	(__formatter_fp::parse): Use _Pres_F for 'F'.
	(__formatter_fp::format): Set __upper for _Pres_F.
	* testsuite/std/format/functions/format.cc: Check formatting of
	infinity and NaN for each presentation type.

libstdc++-v3/ChangeLog:

	* include/Makefile.in: Regenerate.

The following changes the gate to perform vectorization of BB reductions
to use needs_fold_left_reduction_p which in turn requires handling
TYPE_OVERFLOW_UNDEFINED types in the epilogue code generation by
promoting any operations generated there to use unsigned arithmetic.

The following does this, there's currently only v16qi where x86
supports a .REDUC_PLUS reduction for integral modes so I had to
add a x86 specific testcase using GIMPLE IL.

	* tree-vect-slp.cc (vect_slp_check_for_roots): Use
	!needs_fold_left_reduction_p to decide whether we can
	handle the reduction with association.
	(vectorize_slp_instance_root_stmt): For TYPE_OVERFLOW_UNDEFINED
	reductions perform all arithmetic in an unsigned type.

	* gcc.target/i386/vect-reduc-2.c: New testcase.

Test case g++.dg/analyzer/fanalyzer-show-events-in-system-headers.C
introduced by patch ce8cdf5b
emitted a warning for an unused dg-line variable.
This fixes up the blunder.

Signed-off-by: benjamin priour <vultkayn@gcc.gnu.org>

gcc/testsuite/ChangeLog:

	* g++.dg/analyzer/fanalyzer-show-events-in-system-headers.C:
	Remove dg-line var declare_a.

On macOS 14, a guard in <math.h> changed:

-- MacOSX13.3.sdk/usr/include/math.h	2023-04-19 01:54:44
+++ MacOSX14.0.sdk/usr/include/math.h	2023-08-01 08:42:43
@@ -22,0 +23 @@
+
@@ -43 +44 @@
-#if __FLT_EVAL_METHOD__ == 0
+#if __FLT_EVAL_METHOD__ == 0 || __FLT_EVAL_METHOD__ == -1
@@ -49 +50 @@
-#elif __FLT_EVAL_METHOD__ == 2 || __FLT_EVAL_METHOD__ == -1
+#elif __FLT_EVAL_METHOD__ == 2

Therefore the darwin_flt_eval_method fixincludes fix doesn't match any
longer, leading to a large number of testsuite failures like

/private/var/gcc/regression/master/14-gcc/build/gcc/include-fixed/math.h:69:5:
error: #error "Unsupported value of __FLT_EVAL_METHOD__."

where __FLT_EVAL_METHOD__ = 16.

This patch adjusts the fix to allow for both forms.

Tested with make check in fixincludes on x86_64-apple-darwin23.0.0 and
verifying that <math.h> has indeed been fixed as expected.

2023-08-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	fixincludes:
	* inclhack.def (darwin_flt_eval_method): Handle macOS 14 guard
	variant.
	* fixincl.x: Regenerate.
	* tests/base/math.h [DARWIN_FLT_EVAL_METHOD_CHECK]: Update test.

Since Xcode 15 beta 6, ld -v output differs from previous versions:

* macOS 13/Xcode 14:

  @(#)PROGRAM:ld  PROJECT:ld64-857.1

* macOS 14/Xcode 15:

  @(#)PROGRAM:ld  PROJECT:dyld-1015.1

configure cannot handle the new form, so LD64_VERSION isn't set.

This patch fixes this.  The autoconf manual states that sed doesn't
portably support alternation, so I'm using two separate expressions to
extract the version number.

Tested on x86_64-apple-darwin23.0.0.

2023-08-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	gcc:
	* configure.ac (gcc_cv_ld64_version): Allow for dyld in ld -v
	output.
	* configure: Regenerate.

These tests expect to be able to #undef a feature test macro and then
include <version> to get it redefined. But if <version> has already been
included by the <bits/stdc++.h> PCH then including it again does nothing
and the macro remains undefined.

libstdc++-v3/ChangeLog:

	* testsuite/24_iterators/move_iterator/p2520r0.cc: Add no_pch.
	* testsuite/std/format/functions/format.cc: Likewise.
	* testsuite/std/format/functions/format_c++23.cc: Likewise.

The { dg-add-options no_pch } directive is supposed to add a macro
definition that invalidates the PCH file, and ensures that the #include
directives in the test file are processed as written. But the proc that
adds the options actually removes all existing options, cancelling out
any previous dg-options directive.

This means that using no_pch will cause FAILs in a file that relies on
other options set by an earlier dg-options.

The no_pch directive was added for PR libstdc++/21769 where Janis
suggested adding it as return "$flags -D__GLIBCXX__=99999999" but what
was actually committed didn't include the $flags so replaced them.

Additionally, using no_pch  only prevents the precompiled version of
<bits/stdc++.h> from being included, it doesn't prevent the
non-precompiled version being included by -include bits/stdc++.h in the
test flags. Use regsub to filter that out of the options as well.

libstdc++-v3/ChangeLog:

	* testsuite/lib/dg-options.exp (add_options_for_no_pch): Remove
	any "-include bits/stdc++.h" from options and add the macro to
	the existing options instead of replacing them.

This patch would like to support the rounding mode API for the
VFWREDOSUM.VS as the below samples

* __riscv_vfwredosum_vs_f32m1_f64m1_rm
* __riscv_vfwredosum_vs_f32m1_f64m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(widen_freducop): Add frm_opt_type template arg.
	(vfwredosum_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfwredosum_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.

This patch would like to support the rounding mode API for the
VFREDOSUM.VS as the below samples.

* __riscv_vfredosum_vs_f32m1_f32m1_rm
* __riscv_vfredosum_vs_f32m1_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(vfredosum_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfredosum_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-redosum.c: New test.

This patch would like to support the rounding mode API for the
VFREDUSUM.VS as the below samples.

* __riscv_vfredusum_vs_f32m1_f32m1_rm
* __riscv_vfredusum_vs_f32m1_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class freducop): Add frm_op_type template arg.
	(vfredusum_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfredusum_frm): New intrinsic function def.
	* config/riscv/riscv-vector-builtins-shapes.cc
	(struct reduc_alu_frm_def): New class for frm shape.
	(SHAPE): New declaration.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-redusum.c: New test.

This patch would like to support the rounding mode API for the
VFNCVT.F.{X|XU|F}.W as the below samples.

* __riscv_vfncvt_f_x_w_f32m1_rm
* __riscv_vfncvt_f_x_w_f32m1_rm_m
* __riscv_vfncvt_f_xu_w_f32m1_rm
* __riscv_vfncvt_f_xu_w_f32m1_rm_m
* __riscv_vfncvt_f_f_w_f32m1_rm
* __riscv_vfncvt_f_f_w_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfncvt_f): Add frm_op_type template arg.
	(vfncvt_f_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfncvt_f_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test.

This patch would like to support the rounding mode API for the
VFNCVT.XU.F.W as the below samples.

* __riscv_vfncvt_xu_f_w_u16mf2_rm
* __riscv_vfncvt_xu_f_w_u16mf2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(vfncvt_xu_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfncvt_xu_frm): New intrinsic function def.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-ncvt-xu.c: New test.

This patch would like to support the rounding mode API for the
VFNCVT.X.F.W as the below samples.

* __riscv_vfncvt_x_f_w_i16mf2_rm
* __riscv_vfncvt_x_f_w_i16mf2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfncvt_x): Add frm_op_type template arg.
	(BASE): New declaration.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfncvt_x_frm): New intrinsic function def.
	* config/riscv/riscv-vector-builtins-shapes.cc
	(struct narrow_alu_frm_def): New shape function for frm.
	(SHAPE): New declaration.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-ncvt-x.c: New test.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-vextractf64x2-1.c: New test.
	* gcc.target/i386/avx10_1-vextracti64x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vfpclasspd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vfpclassps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vinsertf64x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vinserti64x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vrangepd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vrangeps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vreducepd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vreduceps-1.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512vldqintrin.h: Remove target attribute.
	* config/i386/i386-builtin.def (BDESC):
	Add OPTION_MASK_ISA2_AVX10_1.
	* config/i386/sse.md (VF_AVX512VLDQ_AVX10_1): New.
	(VFH_AVX512VLDQ_AVX10_1): Ditto.
	(VF1_AVX512VLDQ_AVX10_1): Ditto.
	(<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
	Change iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
	(vec_pack<floatprefix>_float_<mode>): Change iterator to
	VI8_AVX512VLDQ_AVX10_1. Remove target check.
	(vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Change iterator to
	VF1_AVX512VLDQ_AVX10_1. Remove target check.
	(vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
	(VI48F_256_DQVL_AVX10_1): Rename from VI48F_256_DQ.
	(avx512vl_vextractf128<mode>): Change iterator to
	VI48F_256_DQVL_AVX10_1. Remove target check.
	(vec_extract_hi_<mode>_mask): Add TARGET_AVX10_1.
	(vec_extract_hi_<mode>): Ditto.
	(avx512vl_vinsert<mode>): Ditto.
	(vec_set_lo_<mode><mask_name>): Ditto.
	(vec_set_hi_<mode><mask_name>): Ditto.
	(avx512dq_rangep<mode><mask_name><round_saeonly_name>): Change
	iterator to VF_AVX512VLDQ_AVX10_1. Remove target check.
	(avx512dq_fpclass<mode><mask_scalar_merge_name>): Change
	iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
	* config/i386/subst.md (mask_avx512dq_condition): Add
	TARGET_AVX10_1.
	(mask_scalar_merge): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-abs-copysign-1.c: New test.
	* gcc.target/i386/avx10_1-vandpd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vandps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtps2qq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtps2uqq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtqq2pd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtqq2ps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtuqq2pd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtuqq2ps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vorpd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vorps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vpmovd2m-1.c: Ditto.
	* gcc.target/i386/avx10_1-vpmovm2d-1.c: Ditto.
	* gcc.target/i386/avx10_1-vpmovm2q-1.c: Ditto.
	* gcc.target/i386/avx10_1-vpmovq2m-1.c: Ditto.
	* gcc.target/i386/avx10_1-vxorpd-1.c: Ditto.
	* gcc.target/i386/avx10_1-vxorps-1.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512vldqintrin.h: Remove target attribute.
	* config/i386/i386-builtin.def (BDESC):
	Add OPTION_MASK_ISA2_AVX10_1.
	* config/i386/i386.cc (standard_sse_constant_opcode): Add TARGET_AVX10_1.
	* config/i386/sse.md: (VI48_AVX512VL_AVX10_1): New.
	(VI48_AVX512VLDQ_AVX10_1): Ditto.
	(VF2_AVX512VL): Remove.
	(VI8_256_512VLDQ_AVX10_1): Rename from VI8_256_512.
	Add TARGET_AVX10_1.
	(*<code><mode>3<mask_name>): Change isa attribute to
	avx10_1_or_avx512dq. Add TARGET_AVX10_1.
	(<code><mode>3): Add TARGET_AVX10_1. Change isa attr
	to avx10_1_or_avx512vl.
	(<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>):
	Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
	(<mask_codefor>avx512dq_cvtps2qqv2di<mask_name>):
	Add TARGET_AVX10_1.
	(<mask_codefor>avx512dq_cvtps2uqq<mode><mask_name><round_name>):
	Change iterator to VI8_256_512VLDQ_AVX10_1. Remove target check.
	(<mask_codefor>avx512dq_cvtps2uqqv2di<mask_name>):
	Add TARGET_AVX10_1.
	(float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
	Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
	(float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
	Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
	(float<floatunssuffix>v4div4sf2<mask_name>):
	Add TARGET_AVX10_1.
	(avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
	(*avx512dq_float<floatunssuffix>v2div2sf2): Ditto.
	(float<floatunssuffix>v2div2sf2): Ditto.
	(float<floatunssuffix>v2div2sf2_mask): Ditto.
	(*float<floatunssuffix>v2div2sf2_mask): Ditto.
	(*float<floatunssuffix>v2div2sf2_mask_1): Ditto.
	(<avx512>_cvt<ssemodesuffix>2mask<mode>):
	Change iterator to VI48_AVX512VLDQ_AVX10_1. Remove target check.
	(<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto.
	(*<avx512>_cvtmask2<ssemodesuffix><mode>):
	Change iterator to VI48_AVX512VL_AVX10_1. Remove target check.
	Change when constraint is enabled.

void foo(_Float16 y, int64_t *i64p)
{
  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
}

zve64f:
foo:
	vsetivli	zero,1,e16,mf4,ta,ma
	vle64.v	v1,0(a0)
	vfmv.s.f	v2,fa0
	vsetvli	zero,zero,e64,m1,ta,ma
	vadd.vv	v1,v1,v1

zve64d:
foo:
	vsetivli	zero,1,e64,m1,ta,ma
	vle64.v	v1,0(a0)
	vfmv.s.f	v2,fa0
	vadd.vv	v1,v1,v1

gcc/ChangeLog:

	PR target/111037
	* config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
	(second_sew_less_than_first_sew_p): Fix bug.
	(first_sew_less_than_second_sew_p): Ditto.

gcc/testsuite/ChangeLog:

	PR target/111037
	* gcc.target/riscv/rvv/base/pr111037-1.c: New test.
	* gcc.target/riscv/rvv/base/pr111037-2.c: New test.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-vandnpd-1.c: New test.
	* gcc.target/i386/avx10_1-vandnps-1.c: Ditto.
	* gcc.target/i386/avx10_1-vbroadcastf32x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vbroadcastf64x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vbroadcasti32x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vbroadcasti64x2-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtpd2qq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvtpd2uqq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvttpd2qq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvttpd2uqq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvttps2qq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vcvttps2uqq-1.c: Ditto.
	* gcc.target/i386/avx10_1-vpmullq-1.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512vldqintrin.h: Remove target attribute.
	* config/i386/i386-builtin.def (BDESC):
	Add OPTION_MASK_ISA2_AVX10_1.
	* config/i386/i386-builtins.cc (def_builtin): Handle AVX10_1.
	* config/i386/i386-expand.cc
	(ix86_check_builtin_isa_match): Ditto.
	(ix86_expand_sse2_mulvxdi3): Add TARGET_AVX10_1.
	* config/i386/i386.md: Add new isa attribute avx10_1_or_avx512dq
	and avx10_1_or_avx512vl.
	* config/i386/sse.md: (VF2_AVX512VLDQ_AVX10_1): New.
	(VF1_128_256VLDQ_AVX10_1): Ditto.
	(VI8_AVX512VLDQ_AVX10_1): Ditto.
	(<sse>_andnot<mode>3<mask_name>):
	Add TARGET_AVX10_1 and change isa attr from avx512dq to
	avx10_1_or_avx512dq.
	(*andnot<mode>3): Add TARGET_AVX10_1 and change isa attr from
	avx512vl to avx10_1_or_avx512vl.
	(fix<fixunssuffix>_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
	Change iterator to VF2_AVX512VLDQ_AVX10_1. Remove target check.
	(fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
	Ditto.
	(ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
	Ditto.
	(fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
	Change iterator to VF1_128_256VLDQ_AVX10_1. Remove target check.
	(avx512dq_fix<fixunssuffix>_truncv2sfv2di2<mask_name>):
	Add TARGET_AVX10_1.
	(fix<fixunssuffix>_truncv2sfv2di2): Ditto.
	(cond_mul<mode>): Change iterator to VI8_AVX10_1_AVX512DQVL.
	Remove target check.
	(avx512dq_mul<mode>3<mask_name>): Ditto.
	(*avx512dq_mul<mode>3<mask_name>): Ditto.
	(VI4F_BRCST32x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
	(<mask_codefor>avx512dq_broadcast<mode><mask_name>):
	Remove target check.
	(VI8F_BRCST64x2): Add TARGET_AVX512DQ and TARGET_AVX10_1.
	(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1):
	Remove target check.
	* config/i386/subst.md (mask_mode512bit_condition): Add TARGET_AVX10_1.
	(mask_avx512vl_condition): Ditto.
	(mask): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Add -mavx10.1.
	* gcc.target/i386/avx-2.c: Ditto.
	* gcc.target/i386/sse-26.c: Skip AVX512VLDQ intrin file.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(ix86_check_avx10_vector_width): New function to check isa_flags
	to emit a warning when there is a conflict in AVX10 options for
	vector width.
	(ix86_handle_option): Add check for avx10.1-256 and avx10.1-512.
	* config/i386/driver-i386.cc (host_detect_local_cpu):
	Do not append -mno-avx10-max-512bit for -march=native.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-15.c: New test.
	* gcc.target/i386/avx10_1-16.c: Ditto.
	* gcc.target/i386/avx10_1-17.c: Ditto.
	* gcc.target/i386/avx10_1-18.c: Ditto.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(ix86_check_avx10): New function to check isa_flags and
	isa_flags_explicit to emit warning when AVX10 is enabled
	by "-m" option.
	(ix86_check_avx512):  New function to check isa_flags and
	isa_flags_explicit to emit warning when AVX512 is enabled
	by "-m" option.
	(ix86_handle_option): Do not change the flags when warning
	is emitted.
	* config/i386/driver-i386.cc (host_detect_local_cpu):
	Do not append -mno-avx10.1 for -march=native.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10_1-11.c: New test.
	* gcc.target/i386/avx10_1-12.c: Ditto.
	* gcc.target/i386/avx10_1-13.c: Ditto.
	* gcc.target/i386/avx10_1-14.c: Ditto.

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features):
	Add avx10_set and version and detect avx10.1.
	(cpu_indicator_init): Handle avx10.1-512.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX10_512BIT_SET): New.
	(OPTION_MASK_ISA2_AVX10_1_SET): Ditto.
	(OPTION_MASK_ISA2_AVX10_512BIT_UNSET): Ditto.
	(OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto.
	(OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10_1.
	(ix86_handle_option): Handle -mavx10.1, -mavx10.1-256 and
	-mavx10.1-512.
	* common/config/i386/i386-cpuinfo.h (enum processor_features):
	Add FEATURE_AVX10_512BIT, FEATURE_AVX10_1 and
	FEATURE_AVX10_512BIT.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
	AVX10_512BIT, AVX10_1 and AVX10_1_512.
	* config/i386/constraints.md (Yk): Add AVX10_1.
	(Yv): Ditto.
	(k): Ditto.
	* config/i386/cpuid.h (bit_AVX10): New.
	(bit_AVX10_256): Ditto.
	(bit_AVX10_512): Ditto.
	* config/i386/i386-c.cc (ix86_target_macros_internal):
	Define AVX10_512BIT and AVX10_1.
	* config/i386/i386-isa.def
	(AVX10_512BIT): Add DEF_PTA(AVX10_512BIT).
	(AVX10_1): Add DEF_PTA(AVX10_1).
	* config/i386/i386-options.cc (isa2_opts): Add -mavx10.1.
	(ix86_valid_target_attribute_inner_p): Handle avx10-512bit, avx10.1
	and avx10.1-512.
	(ix86_option_override_internal): Enable AVX512{F,VL,BW,DQ,CD,BF16,
	FP16,VBMI,VBMI2,VNNI,IFMA,BITALG,VPOPCNTDQ} features for avx10.1-512.
	(ix86_valid_target_attribute_inner_p): Handle AVX10_1.
	* config/i386/i386.cc (ix86_get_ssemov): Add AVX10_1.
	(ix86_conditional_register_usage): Ditto.
	(ix86_hard_regno_mode_ok): Ditto.
	(ix86_rtx_costs): Ditto.
	* config/i386/i386.h (VALID_MASK_AVX10_MODE): New macro.
	* config/i386/i386.opt: Add option -mavx10.1, -mavx10.1-256 and
	-mavx10.1-512.
	* doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
	* doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
	* doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
	and avx10.1-512.

gcc/testsuite/ChangeLog:

	* g++.target/i386/mv33.C: New test.
	* gcc.target/i386/avx10_1-1.c: Ditto.
	* gcc.target/i386/avx10_1-2.c: Ditto.
	* gcc.target/i386/avx10_1-3.c: Ditto.
	* gcc.target/i386/avx10_1-4.c: Ditto.
	* gcc.target/i386/avx10_1-5.c: Ditto.
	* gcc.target/i386/avx10_1-6.c: Ditto.
	* gcc.target/i386/avx10_1-7.c: Ditto.
	* gcc.target/i386/avx10_1-8.c: Ditto.
	* gcc.target/i386/avx10_1-9.c: Ditto.
	* gcc.target/i386/avx10_1-10.c: Ditto.

Follow removal of EVRP and clean up unused defines.

gcc/
	* flag-types.h (vrp_mode): Remove unused.

From: Yanzhang Wang <yanzhang.wang@intel.com>

The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,

shortcut_for_riscv_vrsub_case_1_32:
        vl1re32.v       v1,0(a1)
        vsetvli zero,a2,e32,m1,ta,ma
        vrsub.vi        v1,v1,-1
        vs1r.v  v1,0(a0)
        ret

to,

shortcut_for_riscv_vrsub_case_1_32:
        vl1re32.v       v1,0(a1)
        vsetvli zero,a2,e32,m1,ta,ma
        vnot.v  v1,v1
        vs1r.v  v1,0(a0)
        ret

gcc/ChangeLog:

	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Use
	CONSTM1_RTX.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/simplify-vrsub.c: New test.

Like the support conditional neg (r12-4470-g20dcda98ed376cb61c74b2c71),
this just adds conditional not too.
Also we should be able to turn `(a ? -1 : 0) ^ b` into a conditional
not.

OK? Bootstrapped and tested on x86_64-linux-gnu and aarch64-linux-gnu.

gcc/ChangeLog:

	* internal-fn.def (COND_NOT): New internal function.
	* match.pd (UNCOND_UNARY, COND_UNARY): Add bit_not/not
	to the lists.
	(`vec (a ? -1 : 0) ^ b`): New pattern to convert
	into conditional not.
	* optabs.def (cond_one_cmpl): New optab.
	(cond_len_one_cmpl): Likewise.

gcc/testsuite/ChangeLog:

	PR target/110986
	* gcc.target/aarch64/sve/cond_unary_9.c: New test.