When long double is wider than double, but from_chars is implemented
in terms of double, tests that involve the full precision of long
double are expected to fail.  Mark them as such on aarch64-*-vxworks.


for  libstdc++-v3/ChangeLog

	* testsuite/20_util/from_chars/4.cc: Skip long double test06
	on aarch64-vxworks.
	* testsuite/20_util/to_chars/long_double.cc: Xfail run on
	aarch64-vxworks.

Seemingly, the ptx JIT of CUDA <= 10.2 replaces function pointers in global
variables by NULL if a translation does not contain any executable code. It
works with CUDA 11.1.  The code of this commit is about reverse offload;
having NULL values disables the side of reverse offload during image load.

Solution is the same as found by Thomas for a related issue: Adding a dummy
procedure. Cf. the PR of this issue and Thomas' patch
"nvptx: Support global constructors/destructors via 'collect2'"
https://gcc.gnu.org/pipermail/gcc-patches/2022-December/607749.html



As that approach also works here:

Co-authored-by: Thomas Schwinge <thomas@codesourcery.com>

gcc/
	PR libgomp/108098

	* config/nvptx/mkoffload.cc (process): Emit dummy procedure
	alongside reverse-offload function table to prevent NULL values
	of the function addresses.

I've noticed 4 typos in comments, fixed thusly.

2023-05-05  Jakub Jelinek  <jakub@redhat.com>

	* builtins.cc (do_mpfr_ckconv, do_mpc_ckconv): Fix comment typo,
	mpft_t -> mpfr_t.
	* fold-const-call.cc (do_mpfr_ckconv, do_mpc_ckconv): Likewise.

So it turns out I messed checking which edge was true/false for the diamond
form. The edges, e0 and e1 here are edges from the merge block but the
true/false edges are from the conditional block and with diamond/threeway,
there is a bb inbetween on both edges.
Most of the time, the check that was in match_simplify_replacement would
happen to be correct for diamond form as most of the time the first edge in
the conditional is the edge for the true side of the conditional.
This is why I didn't see the issue during bootstrap/testing.

I added a fragile gimple testcase which exposed the issue. Since there is
no way to specify the order of the edges in the gimple fe, we have to
have forwprop to swap the false/true edges (not order of them, just swapping
true/false flags) and hope not to do cleanupcfg inbetween forwprop and the
first phiopt pass. This is the fragile part really, it is not that we will
produce wrong code, just we won't hit what was the failing case.

OK? Bootstrapped and tested on x86_64-linux-gnu.

	PR tree-optimization/109732

gcc/ChangeLog:

	* tree-ssa-phiopt.cc (match_simplify_replacement): Fix the selection
	of the argtrue/argfalse.

gcc/testsuite/ChangeLog:

	* gcc.dg/pr109732.c: New test.
	* gcc.dg/pr109732-1.c: New test.

There is already an `ABS<a> == 0` to `a == 0` pattern,
this just extends that to ABSU too.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

	PR tree-optimization/109722

gcc/ChangeLog:

	* match.pd: Extend the `ABS<a> == 0` pattern
	to cover `ABSU<a> == 0` too.

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/abs-1.c: New test.

In the testcase the assert fails because we use one member function from
another while we're in the middle of instantiating them all, which is
perfectly fine.  It seems complicated to detect this situation, so let's
remove the assert again.

	PR c++/109658

This reverts commit 95d4c0d2.

gcc/testsuite/ChangeLog:

	* g++.dg/template/local10.C: New test.

The predicates of ashift to lea post-reload splitter were too broad
so the splitter tried to convert the mask shift instruction.  Tighten
operand predicates to match only general registers.

gcc/ChangeLog:

	PR target/109733
	* config/i386/predicates.md (index_reg_operand): New predicate.
	* config/i386/i386.md (ashift to lea spliter): Use
	general_reg_operand and index_reg_operand predicates.

This patch introduces a new quadruple ArithAddOp which is used in
the construction of FOR loop to ensure that when constant folding
is applied it does not concatenate two constant char operands into
a string constant.  Overloading only occurs with constant operands.

gcc/m2/ChangeLog:

	PR modula2/109729
	* gm2-compiler/M2GenGCC.mod (CodeStatement): Detect
	ArithAddOp and call CodeAddChecked.
	(ResolveConstantExpressions): Detect ArithAddOp and call
	FoldArithAdd.
	(FoldArithAdd): New procedure.
	(FoldAdd): Refactor to use FoldArithAdd.
	* gm2-compiler/M2Quads.def (QuadOperator): Add ArithAddOp.
	* gm2-compiler/M2Quads.mod: Remove commented imports.
	(QuadFrame): Changed comments to use GNU coding standards.
	(ArithPlusTok): New global variable.
	(BuildForToByDo): Use ArithPlusTok instead of PlusTok.
	(MakeOp): Detect ArithPlusTok and return ArithAddOp.
	(WriteQuad): Add ArithAddOp clause.
	(WriteOperator): Add ArithAddOp clause.
	(Init): Initialize ArithPlusTok.

gcc/testsuite/ChangeLog:

	PR modula2/109729
	* gm2/pim/run/pass/ForChar.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

Similar to the previous patch, this one converts the high-half versions of the patterns.
With this patch we can remove the UNSPEC_* codes involved entirely.

Bootstrapped and tested on aarch64-none-linux-gnu. Also tested on aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>_insn_le):
	Rename and reimplement with RTL codes to...
	(aarch64_<optab>hn2<mode>_insn_le): .. This.
	(aarch64_r<optab>hn2<mode>_insn_le): New pattern.
	(aarch64_<sur><addsub>hn2<mode>_insn_be): Rename and reimplement with RTL
	codes to...
	(aarch64_<optab>hn2<mode>_insn_be): ... This.
	(aarch64_r<optab>hn2<mode>_insn_be): New pattern.
	(aarch64_<sur><addsub>hn2<mode>): Rename and adjust expander to...
	(aarch64_<optab>hn2<mode>): ... This.
	(aarch64_r<optab>hn2<mode>): New expander.
	* config/aarch64/iterators.md (UNSPEC_ADDHN, UNSPEC_RADDHN,
	UNSPEC_SUBHN, UNSPEC_RSUBHN): Delete unspecs.
	(ADDSUBHN): Delete.
	(sur): Remove handling of the above.
	(addsub): Likewise.

We can implement the halving-narrowing add/sub patterns with standard RTL codes as well rather than relying on unspecs.
This patch handles the low-part ones and the second patch does the high-part ones and removes the unspecs themselves.
The operation ADDHN on V4SI, for example, is represented as (truncate:V4HI ((src1:V4SI + src2:V4SI) >> 16))
and RADDHN as (truncate:V4HI ((src1:V4SI + src2:V4SI + (1 << 15)) >> 16)).
Taking this opportunity I specified the patterns returning the narrow mode and annotated them with the
<vczle><vczbe> define_subst rules to get the vec_concat-zero meta-patterns too. This allows us to simplify
the expanders somewhat too. Tests are added to check that the combinations work.

Bootstrapped and tested on aarch64-none-linux-gnu. Also tested on aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>_insn_le):
	Delete.
	(aarch64_<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
	(aarch64_<sur><addsub>hn<mode>_insn_be): Delete.
	(aarch64_r<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
	(aarch64_<sur><addsub>hn<mode>): Delete.
	(aarch64_<optab>hn<mode>): New define_expand.
	(aarch64_r<optab>hn<mode>): Likewise.
	* config/aarch64/predicates.md (aarch64_simd_raddsubhn_imm_vec):
	New predicate.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/simd/pr99195_4.c: New test.

This patch moves several tests introduced by the following patch:

  https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616939.html
  commit r14-325-gcacf65d74463600815773255e8b82b4043432bd7

into the proper location for OpenACC testing (thanks to Thomas for
spotting my mistake!), and also fixes a few additional problems --
missing diagnostics for non-pointer attaches, and a case where a pointer
was incorrectly dereferenced. Tests are also adjusted for vector-length
warnings on nvidia accelerators.

2023-04-29  Julian Brown  <julian@codesourcery.com>

	PR fortran/109622

gcc/fortran/
	* openmp.cc (resolve_omp_clauses): Add diagnostic for
	non-pointer/non-allocatable attach/detach.
	* trans-openmp.cc (gfc_trans_omp_clauses): Remove dereference for
	pointer-to-scalar derived type component attach/detach.  Fix
	attach/detach handling for descriptors.

gcc/testsuite/
	* gfortran.dg/goacc/pr109622-5.f90: New test.
	* gfortran.dg/goacc/pr109622-6.f90: New test.

libgomp/
	* testsuite/libgomp.fortran/pr109622.f90: Move test...
	* testsuite/libgomp.oacc-fortran/pr109622.f90: ...to here. Ignore
	vector length warning.
	* testsuite/libgomp.fortran/pr109622-2.f90: Move test...
	* testsuite/libgomp.oacc-fortran/pr109622-2.f90: ...to here.  Add
	missing copyin/copyout variable. Ignore vector length warnings.
	* testsuite/libgomp.fortran/pr109622-3.f90: Move test...
	* testsuite/libgomp.oacc-fortran/pr109622-3.f90: ...to here.  Ignore
	vector length warnings.
	* testsuite/libgomp.oacc-fortran/pr109622-4.f90: New test.

libstdc++-v3/ChangeLog:

	* doc/xml/manual/abi.xml (abi.versioning.history): Document
	libstdc++.so.6.0.32 and GLIBCXX_3.4.32 version.
	* doc/html/manual/abi.html: Regenerate.

GCC_11.0 is an aarch64-specific outlier.

libstdc++-v3/ChangeLog:

	* doc/xml/manual/abi.xml (abi.versioning.history): Add
	GCC_7.0.0, GCC_9.0.0, GCC_11.0, GCC_12.0.0, GCC_13.0.0 for
	libgcc_s.

While looking at differences between what minmax_replacement
and match_simplify_replacement does. I noticed that they sometimes
chose different edges to remove. I decided we should be able to do
better and be able to remove both empty basic blocks in the
case of match_simplify_replacement as that moves the statements.

This also updates the testcases as now match_simplify_replacement
will remove the unused MIN/MAX_EXPR and they were checking for
those.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

	* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Handle
	diamond form bb with forwarder only empty blocks better.

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/minmax-15.c: Update test.
	* gcc.dg/tree-ssa/minmax-16.c: Update test.
	* gcc.dg/tree-ssa/minmax-3.c: Update test.
	* gcc.dg/tree-ssa/minmax-4.c: Update test.
	* gcc.dg/tree-ssa/minmax-5.c: Update test.
	* gcc.dg/tree-ssa/minmax-8.c: Update test.

While improving replace_phi_edge_with_variable for the diamond formed bb
case, I need a way to copy phi entries from one edge to another as I am
removing a forwarding bb inbetween. I was pointed out that jump threading
code had copy_phi_arg_into_existing_phi which I can use.
I also noticed that both gimple_duplicate_sese_tail and
remove_forwarder_block have similar code so it makes sense to use that function
in those two locations too.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

	* tree-ssa-threadupdate.cc (copy_phi_arg_into_existing_phi): Move to ...
	* tree-cfg.cc (copy_phi_arg_into_existing_phi): Here and remove static.
	(gimple_duplicate_sese_tail): Use copy_phi_arg_into_existing_phi instead
	of an inline version of it.
	* tree-cfgcleanup.cc (remove_forwarder_block): Likewise.
	* tree-cfg.h (copy_phi_arg_into_existing_phi): New declaration.

When I added the dce_ssa_names argument, I didn't realize bitmap was a
pointer so I used the default argument value as auto_bitmap(). But
instead we could just use nullptr and check if it was a nullptr
before calling simple_dce_from_worklist.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

	* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Change
	the default argument value for dce_ssa_names to nullptr.
	Check to make sure dce_ssa_names is a non-nullptr before
	calling simple_dce_from_worklist.

Use the same approach as in register_no_elim_operand predicate, but also
reject stack_pointer_rtx operands.

gcc/ChangeLog:

	* config/i386/predicates.md (index_register_operand): Reject
	arg_pointer_rtx, frame_pointer_rtx, stack_pointer_rtx and
	VIRTUAL_REGISTER_P operands.  Allow subregs of memory before reload.
	(call_register_no_elim_operand): Rewrite as ...
	(call_register_operand): ... this.
	(call_insn_operand): Use call_register_operand predicate.

When fixing PR109672 I noticed we let SImode AND through when
target_support_p even though it isn't word_mode and I didn't want to
change that but had to catch the case where SImode PLUS is supported
but emulated vectors rely on it being word_mode.  The following
makes sure to preserve the word_mode check when !target_support_p
to avoid excessive lowering later even for bit operations.

	PR tree-optimization/109721
	* tree-vect-stmts.cc (vectorizable_operation): Make sure
	to test word_mode for all !target_support_p operations.

We're now moving onto various simple ternary instructions, including some lane forms.
These include intrinsics that map down to mla, mls, fma, aba, bsl instructions.
Tests are added for lane 0 and lane 1 as for some of these instructions the lane 0 variants
use separate simpler patterns that need a separate annotation.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (aarch64_<su>aba<mode>): Rename to...
	(aarch64_<su>aba<mode><vczle><vczbe>): ... This.
	(aarch64_mla<mode>): Rename to...
	(aarch64_mla<mode><vczle><vczbe>): ... This.
	(*aarch64_mla_elt<mode>): Rename to...
	(*aarch64_mla_elt<mode><vczle><vczbe>): ... This.
	(*aarch64_mla_elt_<vswap_width_name><mode>): Rename to...
	(*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
	(aarch64_mla_n<mode>): Rename to...
	(aarch64_mla_n<mode><vczle><vczbe>): ... This.
	(aarch64_mls<mode>): Rename to...
	(aarch64_mls<mode><vczle><vczbe>): ... This.
	(*aarch64_mls_elt<mode>): Rename to...
	(*aarch64_mls_elt<mode><vczle><vczbe>): ... This.
	(*aarch64_mls_elt_<vswap_width_name><mode>): Rename to...
	(*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
	(aarch64_mls_n<mode>): Rename to...
	(aarch64_mls_n<mode><vczle><vczbe>): ... This.
	(fma<mode>4): Rename to...
	(fma<mode>4<vczle><vczbe>): ... This.
	(*aarch64_fma4_elt<mode>): Rename to...
	(*aarch64_fma4_elt<mode><vczle><vczbe>): ... This.
	(*aarch64_fma4_elt_<vswap_width_name><mode>): Rename to...
	(*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
	(*aarch64_fma4_elt_from_dup<mode>): Rename to...
	(*aarch64_fma4_elt_from_dup<mode><vczle><vczbe>): ... This.
	(fnma<mode>4): Rename to...
	(fnma<mode>4<vczle><vczbe>): ... This.
	(*aarch64_fnma4_elt<mode>): Rename to...
	(*aarch64_fnma4_elt<mode><vczle><vczbe>): ... This.
	(*aarch64_fnma4_elt_<vswap_width_name><mode>): Rename to...
	(*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
	(*aarch64_fnma4_elt_from_dup<mode>): Rename to...
	(*aarch64_fnma4_elt_from_dup<mode><vczle><vczbe>): ... This.
	(aarch64_simd_bsl<mode>_internal): Rename to...
	(aarch64_simd_bsl<mode>_internal<vczle><vczbe>): ... This.
	(*aarch64_simd_bsl<mode>_alt): Rename to...
	(*aarch64_simd_bsl<mode>_alt<vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_3.c: New test.

More pattern annotations and tests to eliminate redundant vec-concat with zero instructions.
These are for the abd family of instructions and the pairwise floating-point max/min and fadd
operations too.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>): Rename to...
	(aarch64_<su>abd<mode><vczle><vczbe>): ... This.
	(fabd<mode>3): Rename to...
	(fabd<mode>3<vczle><vczbe>): ... This.
	(aarch64_<optab>p<mode>): Rename to...
	(aarch64_<optab>p<mode><vczle><vczbe>): ... This.
	(aarch64_faddp<mode>): Rename to...
	(aarch64_faddp<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_1.c: Add testing for more binary ops.
	* gcc.target/aarch64/simd/pr99195_2.c: Add testing for more binary ops.

gcc/ChangeLog:

	* gcov.cc (GCOV_JSON_FORMAT_VERSION): New definition.
	(print_version): Use it.
	(generate_results): Likewise.

The following adds a testcase for PR109724 which was caused by
backporting r13-2375-gbe1b42de9c151d and fixed by r11-199-g2b42509f8b7bdf.

	PR tree-optimization/109724
	* g++.dg/torture/pr109724.C: New testcase.

The following renames last_stmt to last_nondebug_stmt which is
what it really does.

	* tree-cfg.h (last_stmt): Rename to ...
	(last_nondebug_stmt): ... this.
	* tree-cfg.cc (last_stmt): Rename to ...
	(last_nondebug_stmt): ... this.
	(assign_discriminators): Adjust.
	(group_case_labels_stmt): Likewise.
	(gimple_can_duplicate_bb_p): Likewise.
	(execute_fixup_cfg): Likewise.
	* auto-profile.cc (afdo_propagate_circuit): Likewise.
	* gimple-range.cc (gimple_ranger::range_on_exit): Likewise.
	* omp-expand.cc (workshare_safe_to_combine_p): Likewise.
	(determine_parallel_type): Likewise.
	(adjust_context_and_scope): Likewise.
	(expand_task_call): Likewise.
	(remove_exit_barrier): Likewise.
	(expand_omp_taskreg): Likewise.
	(expand_omp_for_init_counts): Likewise.
	(expand_omp_for_init_vars): Likewise.
	(expand_omp_for_static_chunk): Likewise.
	(expand_omp_simd): Likewise.
	(expand_oacc_for): Likewise.
	(expand_omp_for): Likewise.
	(expand_omp_sections): Likewise.
	(expand_omp_atomic_fetch_op): Likewise.
	(expand_omp_atomic_cas): Likewise.
	(expand_omp_atomic): Likewise.
	(expand_omp_target): Likewise.
	(expand_omp): Likewise.
	(omp_make_gimple_edges): Likewise.
	* trans-mem.cc (tm_region_init): Likewise.
	* tree-inline.cc (redirect_all_calls): Likewise.
	* tree-parloops.cc (gen_parallel_loop): Likewise.
	* tree-ssa-loop-ch.cc (do_while_loop_p): Likewise.
	* tree-ssa-loop-ivcanon.cc (canonicalize_loop_induction_variables):
	Likewise.
	* tree-ssa-loop-ivopts.cc (stmt_after_ip_normal_pos): Likewise.
	(may_eliminate_iv): Likewise.
	* tree-ssa-loop-manip.cc (standard_iv_increment_position): Likewise.
	* tree-ssa-loop-niter.cc (do_warn_aggressive_loop_optimizations):
	Likewise.
	(estimate_numbers_of_iterations): Likewise.
	* tree-ssa-loop-split.cc (compute_added_num_insns): Likewise.
	* tree-ssa-loop-unswitch.cc (get_predicates_for_bb): Likewise.
	(set_predicates_for_bb): Likewise.
	(init_loop_unswitch_info): Likewise.
	(hoist_guard): Likewise.
	* tree-ssa-phiopt.cc (match_simplify_replacement): Likewise.
	(minmax_replacement): Likewise.
	* tree-ssa-reassoc.cc (update_range_test): Likewise.
	(optimize_range_tests_to_bit_test): Likewise.
	(optimize_range_tests_var_bound): Likewise.
	(optimize_range_tests): Likewise.
	(no_side_effect_bb): Likewise.
	(suitable_cond_bb): Likewise.
	(maybe_optimize_range_tests): Likewise.
	(reassociate_bb): Likewise.
	* tree-vrp.cc (rvrp_folder::pre_fold_bb): Likewise.

The following testcase ICEs because STV replaces there
(debug_insn 114 47 51 8 (var_location:TI D#3 (reg:TI 91 [ p ])) -1
     (nil))
with
(debug_insn 114 47 51 8 (var_location:TI D#3 (reg:V1TI 91 [ p ])) -1
     (nil))
which is invalid because of the mode mismatch.
STV has fix_debug_reg_uses function which is supposed to fix this up
and adjust such debug insns into
(debug_insn 114 47 51 8 (var_location:TI D#3 (subreg:TI (reg:V1TI 91 [ p ]) 0)) -1
     (nil))
but it doesn't trigger here.
The IL before stv1 has:
(debug_insn 114 47 51 8 (var_location:TI D#3 (reg:TI 91 [ p ])) -1
     (nil))
...
(insn 63 62 64 8 (set (mem/c:TI (reg/f:DI 89 [ .result_ptr ]) [0 <retval>.mStorage+0 S16 A32])
        (reg:TI 91 [ p ])) "pr109676.C":4:48 87 {*movti_internal}
     (expr_list:REG_DEAD (reg:TI 91 [ p ])
        (nil)))
in bb 8 and
(insn 97 96 98 9 (set (reg:TI 91 [ p ])
        (mem/c:TI (plus:DI (reg/f:DI 19 frame)
                (const_int -32 [0xffffffffffffffe0])) [0 p+0 S16 A128])) "pr109676.C":26:12 87 {*movti_internal}
     (nil))
(insn 98 97 99 9 (set (mem/c:TI (plus:DI (reg/f:DI 19 frame)
                (const_int -64 [0xffffffffffffffc0])) [0 tmp+0 S16 A128])
        (reg:TI 91 [ p ])) "pr109676.C":26:12 87 {*movti_internal}
     (nil))
in bb9.
PUT_MODE on a REG is done in two spots in timode_scalar_chain::convert_insn,
one is:
  switch (GET_CODE (dst))
    {
    case REG:
      if (GET_MODE (dst) == TImode)
        {
          PUT_MODE (dst, V1TImode);
          fix_debug_reg_uses (dst);
        }
      if (GET_MODE (dst) == V1TImode)
when seeing the REG in SET_DEST and another one the hunk the patch adjusts.
Because bb 8 comes first in the order the pass walks the bbs, we first
notice the TImode pseudo on insn 63 where it is SET_SRC, use PUT_MODE there
unconditionally, so for a shared REG it changes all other uses in the IL,
and then don't call fix_debug_reg_uses because DF_REG_DEF_CHAIN (REGNO (src))
is non-NULL - the REG is set in insn 97 but we haven't processed it yet.
Later on we process insn 97, but because the REG in SET_DEST already has
V1TImode, we don't do anything, even when the src handling code earlier
relied on it being done.

The following patch fixes this by using similar code for both dst and src,
in particular calling fix_debug_reg_uses once when we actually change REG
mode from TImode to V1TImode, and not later on.

2023-05-04  Jakub Jelinek  <jakub@redhat.com>

	PR debug/109676
	* config/i386/i386-features.cc (timode_scalar_chain::convert_insn):
	If src is REG, change its mode to V1TImode and call fix_debug_reg_uses
	for it only if it still has TImode.  Don't decide whether to call
	fix_debug_reg_uses based on whether SRC is ever set or not.

	* g++.target/i386/pr109676.C: New test.

This kind of transformation seems pretty generic and might be a
candidate for adding to the middle-end, perhaps as part of combine.

I noticed these happened more often for LRA, which is the reason I
went on this track of low-hanging-fruit-microoptimizations that are
such an itch when noticing them, inspecting generated code for libgcc.
Unfortunately, this one improves coremark only by a few cycles at the
beginning or end (<0.0005%) for cris-elf -march=v10.  The size of the
coremark code is down by 0.4% (0.22% pre-lra).

Using an iterator from the start because other binary operations will
be added and their define_peephole2's would look exactly the same for
the .md part.

Some existing and-peephole2-related tests suffered, because many of
them were using patterns with only contiguous 1:s in them: adjusted.
Also, spotted and fixed, by adding a space, some
scan-assembler-strings that were prone to spurious identifier or file
name matches.

gcc:
	* config/cris/cris.cc (cris_split_constant): New function.
	* config/cris/cris.md (splitop): New iterator.
	(opsplit1): New define_peephole2.
	* config/cris/cris-protos.h (cris_split_constant): Declare.
	(cris_splittable_constant_p): New macro.

gcc/testsuite:
	* gcc.target/cris/peep2-andsplit1.c: New test.
	* gcc.target/cris/peep2-andu1.c, gcc.target/cris/peep2-andu2.c,
	gcc.target/cris/peep2-xsrand.c, gcc.target/cris/peep2-xsrand2.c:
	Adjust values to avoid interference with "opsplit1" with AND.  Add
	whitespace to match-strings that may be confused with identifiers
	or file names.

This has no effect on arith-rand-ll (which suffers badly from LRA) and
marginal effects (0.01% improvement) on coremark, but the size of
coremark shrinks by 0.2%.  An earlier version was tested with a tree
around 2023-03 which showed (marginally) that ALL_REGS is preferable
to GENERAL_REGS.

	* config/cris/cris.cc (TARGET_SPILL_CLASS): Define
	to ALL_REGS.

The implementation of gcc/m2/gm2-libs/DynamicStrings.mod:writeAddress
is non portable as it casts a void * into an unsigned long int.  This
procedure has been re-implemented to use snprintf.  As it is a library
the support tools 'mc' and 'pge' have been rebuilt.  There have been
linking changes in the library and the underlying boolean type is now
bool since the last rebuild hence the size of the patch.

gcc/m2/ChangeLog:

	PR modula2/109675
	* Make-lang.in (MC-LIB-DEFS): Remove M2LINK.def.
	(BUILD-PGE-O): Remove GM2LINK.o.
	* Make-maintainer.in (PPG-DEFS): New define.
	(PPG-LIB-DEFS): Remove M2LINK.def.
	(BUILD-BOOT-PPG-H): Add PPGDEF .h files.
	(m2/ppg$(exeext)): Remove M2LINK.o
	(PGE-DEPS): New define.
	(m2/pg$(exeext)): Remove M2LINK.o.
	(m2/gm2-pge-boot/$(SRC_PREFIX)%.o): Add -Im2/gm2-pge-boot.
	(m2/pge$(exeext)): Remove M2LINK.o.
	(pge-maintainer): Re-implement.
	(pge-libs-push): Re-implement.
	(m2/m2obj3/cc1gm2$(exeext)): Remove M2LINK.o.
	* gm2-libs/DynamicStrings.mod (writeAddress): Re-implement
	using snprintf.
	* gm2-libs/M2Dependent.mod: Remove commented out imports.
	* mc-boot/GDynamicStrings.cc: Rebuild.
	* mc-boot/GFIO.cc: Rebuild.
	* mc-boot/GFormatStrings.cc: Rebuild.
	* mc-boot/GM2Dependent.cc: Rebuild.
	* mc-boot/GM2Dependent.h: Rebuild.
	* mc-boot/GM2RTS.cc: Rebuild.
	* mc-boot/GM2RTS.h: Rebuild.
	* mc-boot/GRTExceptions.cc: Rebuild.
	* mc-boot/GRTint.cc: Rebuild.
	* mc-boot/GSFIO.cc: Rebuild.
	* mc-boot/GStringConvert.cc: Rebuild.
	* mc-boot/Gdecl.cc: Rebuild.
	* pge-boot/GASCII.cc: Rebuild.
	* pge-boot/GASCII.h: Rebuild.
	* pge-boot/GArgs.cc: Rebuild.
	* pge-boot/GArgs.h: Rebuild.
	* pge-boot/GAssertion.cc: Rebuild.
	* pge-boot/GAssertion.h: Rebuild.
	* pge-boot/GBreak.h: Rebuild.
	* pge-boot/GCmdArgs.h: Rebuild.
	* pge-boot/GDebug.cc: Rebuild.
	* pge-boot/GDebug.h: Rebuild.
	* pge-boot/GDynamicStrings.cc: Rebuild.
	* pge-boot/GDynamicStrings.h: Rebuild.
	* pge-boot/GEnvironment.h: Rebuild.
	* pge-boot/GFIO.cc: Rebuild.
	* pge-boot/GFIO.h: Rebuild.
	* pge-boot/GFormatStrings.h:: Rebuild.
	* pge-boot/GFpuIO.h:: Rebuild.
	* pge-boot/GIO.cc: Rebuild.
	* pge-boot/GIO.h: Rebuild.
	* pge-boot/GIndexing.cc: Rebuild.
	* pge-boot/GIndexing.h: Rebuild.
	* pge-boot/GLists.cc: Rebuild.
	* pge-boot/GLists.h: Rebuild.
	* pge-boot/GM2Dependent.cc: Rebuild.
	* pge-boot/GM2Dependent.h: Rebuild.
	* pge-boot/GM2EXCEPTION.cc: Rebuild.
	* pge-boot/GM2EXCEPTION.h: Rebuild.
	* pge-boot/GM2RTS.cc: Rebuild.
	* pge-boot/GM2RTS.h: Rebuild.
	* pge-boot/GNameKey.cc: Rebuild.
	* pge-boot/GNameKey.h: Rebuild.
	* pge-boot/GNumberIO.cc: Rebuild.
	* pge-boot/GNumberIO.h: Rebuild.
	* pge-boot/GOutput.cc: Rebuild.
	* pge-boot/GOutput.h: Rebuild.
	* pge-boot/GPushBackInput.cc: Rebuild.
	* pge-boot/GPushBackInput.h: Rebuild.
	* pge-boot/GRTExceptions.cc: Rebuild.
	* pge-boot/GRTExceptions.h: Rebuild.
	* pge-boot/GSArgs.h: Rebuild.
	* pge-boot/GSEnvironment.h: Rebuild.
	* pge-boot/GSFIO.cc: Rebuild.
	* pge-boot/GSFIO.h: Rebuild.
	* pge-boot/GSYSTEM.h: Rebuild.
	* pge-boot/GScan.h: Rebuild.
	* pge-boot/GStdIO.cc: Rebuild.
	* pge-boot/GStdIO.h: Rebuild.
	* pge-boot/GStorage.cc: Rebuild.
	* pge-boot/GStorage.h: Rebuild.
	* pge-boot/GStrCase.cc: Rebuild.
	* pge-boot/GStrCase.h: Rebuild.
	* pge-boot/GStrIO.cc: Rebuild.
	* pge-boot/GStrIO.h: Rebuild.
	* pge-boot/GStrLib.cc: Rebuild.
	* pge-boot/GStrLib.h: Rebuild.
	* pge-boot/GStringConvert.h: Rebuild.
	* pge-boot/GSymbolKey.cc: Rebuild.
	* pge-boot/GSymbolKey.h: Rebuild.
	* pge-boot/GSysExceptions.h: Rebuild.
	* pge-boot/GSysStorage.cc: Rebuild.
	* pge-boot/GSysStorage.h: Rebuild.
	* pge-boot/GTimeString.h: Rebuild.
	* pge-boot/GUnixArgs.h: Rebuild.
	* pge-boot/Gbnflex.cc: Rebuild.
	* pge-boot/Gbnflex.h: Rebuild.
	* pge-boot/Gdtoa.h: Rebuild.
	* pge-boot/Gerrno.h: Rebuild.
	* pge-boot/Gldtoa.h: Rebuild.
	* pge-boot/Glibc.h: Rebuild.
	* pge-boot/Glibm.h: Rebuild.
	* pge-boot/Gpge.cc: Rebuild.
	* pge-boot/Gtermios.h: Rebuild.
	* pge-boot/Gwrapc.h: Rebuild.
	* mc-boot/GM2LINK.h: Removed.
	* pge-boot/GM2LINK.cc: Removed.
	* pge-boot/GM2LINK.h: Removed.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

This shows no difference neither in arith-rand-ll nor coremark
numbers.  Comparing libgcc and newlib libc before/after, the only
difference can be seen in a few functions where it's mostly neutral
(newlib's _svfprintf_r et al) and one function (__gdtoa), which
improves ever so slightly (four bytes less; one load less, but one
instruction reading from memory instead of a register).

	* config/cris/cris.cc (cris_side_effect_mode_ok): Use
	lra_in_progress, not reload_in_progress.
	* config/cris/cris.md ("movdi", "*addi_reload"): Ditto.
	* config/cris/constraints.md ("Q"): Ditto.

This is an ABI problem on powerpc64le-linux, introduced in 13.1.
When libstdc++ is configured against old glibc, the
_ZSt10from_charsPKcS0_RDF128_St12chars_format@@GLIBCXX_3.4.31
_ZSt8to_charsPcS_DF128_@@GLIBCXX_3.4.31
_ZSt8to_charsPcS_DF128_St12chars_format@@GLIBCXX_3.4.31
_ZSt8to_charsPcS_DF128_St12chars_formati@@GLIBCXX_3.4.31
symbols are exported from the library, while when it is configured against
new enough glibc, those symbols aren't exported and we export instead
_ZSt10from_charsPKcS0_Ru9__ieee128St12chars_format@@GLIBCXX_IEEE128_3.4.29
_ZSt8to_charsPcS_u9__ieee128@@GLIBCXX_IEEE128_3.4.29
_ZSt8to_charsPcS_u9__ieee128St12chars_format@@GLIBCXX_IEEE128_3.4.29
_ZSt8to_charsPcS_u9__ieee128St12chars_formati@@GLIBCXX_IEEE128_3.4.29
together with various other @@GLIBCXX_IEEE128_3.4.{29,30,31} and
@@CXXABI_IEEE128_1.3.13 symbols.  The idea was that those *IEEE128* symbol
versions (similarly to *LDBL* symbol versions) are optional (but if it
appears, all symbols from it up to the version of the library appears),
but the base appears always.
My _Float128 from_chars/to_chars changes unfortunately broke this.
I believe nothing really uses those symbols if libstdc++ has been
configured against old glibc, so if 13.1 wasn't already released, it might
be best to make sure they aren't exported on powerpc64le-linux.
But as they were exported, I think the best resolution for this ABI
difference is to add those 4 symbols as aliases to the
GLIBCXX_IEEE128_3.4.29 *u9__ieee128* symbols, which the following patch
does.

2023-05-03  Jakub Jelinek  <jakub@redhat.com>

	* src/c++17/floating_from_chars.cc
	(_ZSt10from_charsPKcS0_RDF128_St12chars_format): New alias to
	_ZSt10from_charsPKcS0_Ru9__ieee128St12chars_format.
	* src/c++17/floating_to_chars.cc (_ZSt8to_charsPcS_DF128_): New alias to
	_ZSt8to_charsPcS_u9__ieee128.
	(_ZSt8to_charsPcS_DF128_St12chars_format): New alias to
	_ZSt8to_charsPcS_u9__ieee128St12chars_format.
	(_ZSt8to_charsPcS_DF128_St12chars_formati): New alias to
	_ZSt8to_charsPcS_u9__ieee128St12chars_formati.
	* config/abi/post/powerpc64le-linux-gnu/baseline_symbols.txt: Updated.

As discussed on IRC, my _Float128/_Float64x support changes broke
abi.exp testing on powerpc64-linux.

The
_ZTIDF128_@@CXXABI_1.3.14
_ZTIDF64x@@CXXABI_1.3.14
_ZTIPDF128_@@CXXABI_1.3.14
_ZTIPDF64x@@CXXABI_1.3.14
_ZTIPKDF128_@@CXXABI_1.3.14
_ZTIPKDF64x@@CXXABI_1.3.14
symbols only appear on powerpc64le-linux (both when building against
very old glibcs as well as contemporary glibcs), while they don't
appear on powerpc64-linux, because the latter never has _Float128 or
_Float64x support.

But we were using the same baseline_symbols.txt file for both
powerpc64-linux and powerpc64le-linux, even when it contained quite a lot
of stuff specific to the latter; but that was just the IEEE128 related
stuff that appears only when configured against not very old glibc.

The following patch keeps those exports as is and just splits the
config/abi/post/ files, copies the current one to powerpc64le-linux
unmodified and removes the above mentioned symbols plus all
GLIBCXX_IEEE128_3.4.{29,30,31} and CXXABI_IEEE128_1.3.13 symbols
from the powerpc64-linux version.

2023-05-03  Jakub Jelinek  <jakub@redhat.com>

	* configure.host (abi_baseline_pair): Use powerpc64le-linux-gnu
	rather than powerpc64-linux-gnu for powerpc64le*-linux*.
	* config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Remove
	_ZTI*DF128_, _ZTI*DF64x symbols and symbols in
	GLIBCXX_IEEE128_3.4.{29,30,31} and CXXABI_IEEE128_1.3.13 symbol
	versions.
	* config/abi/post/powerpc64le-linux-gnu/baseline_symbols.txt: New
	file.

A bug in the simplification I did around 91618; at this point X<int>::f has
DECL_IMPLICIT_INSTANTIATION set, but we've already identified what template
it corresponds to, so we don't want to call check_explicit_specialization.

To distinguish this case we need to look at DECL_TI_TEMPLATE.  grokfndecl
has for a long time set it to the OVERLOAD in this case, while the new cases
I added for 91618 were leaving DECL_TEMPLATE_INFO null; let's adjust them to
match.

	PR c++/91618
	PR c++/109649

gcc/cp/ChangeLog:

	* friend.cc (do_friend): Don't call check_explicit_specialization if
	DECL_TEMPLATE_INFO is already set.
	* decl2.cc (check_classfn): Set DECL_TEMPLATE_INFO.
	* name-lookup.cc (set_decl_namespace): Likewise.

gcc/testsuite/ChangeLog:

	* g++.dg/template/friend77.C: New test.

While looking to move substitute_and_fold_engine
over to use simple_dce_from_worklist, I noticed
that we don't record the stats of the removed stmts/phis.
So this does that.

OK? Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

	* tree-ssa-dce.cc (simple_dce_from_worklist): Record
	stats on removed number of statements and phis.

The old legacy code allowed building ranges of unknown types so passes
like IPA could build and propagate VARYING.  For now it's easiest to
allow the old behavior, it's not like you can do anything with these
ranges except build them and copy them.

Eventually we should convert all users of set_varying() to use
supported types.  I will address this in my upcoming IPA work.

	PR tree-optimization/109711

gcc/ChangeLog:

	* value-range.cc (irange::verify_range): Allow types of
	error_mark_node.

When instrumentation is requested via -fsanitize-coverage=trace-pc, GCC
emits calls of __sanitizer_cov_trace_pc callback in each basic block.
This callback is supposed to be implemented by the user, and should be
able to identify the containing basic block by inspecting its return
address. Tailcalling the callback prevents that, so disallow it.

gcc/ChangeLog:

	PR sanitizer/90746
	* calls.cc (can_implement_as_sibling_call_p): Reject calls
	to __sanitizer_cov_trace_pc.

gcc/testsuite/ChangeLog:

	PR sanitizer/90746
	* gcc.dg/sancov/basic0.c: Verify absence of tailcall.

aarch64_function_arg_alignment has traditionally taken the alignment
of a scalar type T from TYPE_ALIGN (TYPE_MAIN_VARIANT (T)).  This is
supposed to discard any user alignment and give the alignment of the
underlying fundamental type.

PR109661 shows that this did the wrong thing for enums with
a defined underlying type, because:

(1) The enum itself could be aligned, using attributes.
(2) The enum would pick up any user alignment on the underlying type.

We get the right behaviour if we look at the TYPE_MAIN_VARIANT
of the underlying type instead.

As always, this affects register and stack arguments differently,
because:

(a) The code that handles register arguments only considers the
    alignment of types that occupy two registers, whereas the
    stack alignment is applied regardless of size.

(b) The code that handles register arguments tests the alignment
    for equality with 16 bytes, so that (unexpected) greater alignments
    are ignored.  The code that handles stack arguments instead caps the
    alignment to 16 bytes.

There is now (since GCC 13) an assert to trap the difference between
(a) and (b), which is how the new incompatiblity showed up.

Clang alredy handled the testcases correctly, so this patch aligns
the GCC behaviour with the Clang behaviour.

I'm planning to remove the asserts on the branches, since we don't
want to change the ABI there.

gcc/
	PR target/109661
	* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Add
	a new ABI break parameter for GCC 14.  Set it to the alignment
	of enums that have an underlying type.  Take the true alignment
	of such enums from the TYPE_ALIGN of the underlying type's
	TYPE_MAIN_VARIANT.
	(aarch64_function_arg_boundary): Update accordingly.
	(aarch64_layout_arg, aarch64_gimplify_va_arg_expr): Likewise.
	Warn about ABI differences.

gcc/testsuite/
	* g++.target/aarch64/pr109661-1.C: New test.
	* g++.target/aarch64/pr109661-2.C: Likewise.
	* g++.target/aarch64/pr109661-3.C: Likewise.
	* g++.target/aarch64/pr109661-4.C: Likewise.
	* gcc.target/aarch64/pr109661-1.c: Likewise.

aarch64_function_arg_alignment has two related abi_break
parameters: abi_break for a change in GCC 9, and abi_break_packed
for a related follow-on change in GCC 13.  In a sense, abi_break_packed
is a "subfix" of abi_break.

PR109661 now requires a third ABI break that is independent
of the other two.  Having abi_break for the GCC 9 break and
abi_break_<something> for the GCC 13 and GCC 14 breaks might
give the impression that they're all related, and that the GCC 14
fix (like the GCC 13 fix) is a "subfix" of the GCC 9 one.
It therefore seemed like a good idea to rename the existing
variables first.

It would be difficult to choose names that describe briefly and
precisely what went wrong in each case.  The next best thing
seemed to be to name them after the relevant GCC version.
(Of course, this might break down in future if we need two
independent fixes in the same version.  Let's hope not.)

I wondered about putting all the variables in a structure,
but one advantage of using independent variables is that it's
harder to forget to update a caller.  Maybe a fourth parameter
would be a tipping point.

gcc/
	PR target/109661
	* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Rename
	ABI break variables to abi_break_gcc_9 and abi_break_gcc_13.
	(aarch64_layout_arg, aarch64_function_arg_boundary): Likewise.
	(aarch64_gimplify_va_arg_expr): Likewise.

Implement vhaddq, vhsubq, vmulhq, vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq using the new MVE builtins framework.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_NO_F)
	(FUNCTION_WITHOUT_N_NO_F, FUNCTION_WITH_M_N_NO_U_F): New.
	(vhaddq, vhsubq, vmulhq, vqaddq, vqsubq, vqdmulhq, vrhaddq)
	(vrmulhq): New.
	* config/arm/arm-mve-builtins-base.def (vhaddq, vhsubq, vmulhq)
	(vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
	* config/arm/arm-mve-builtins-base.h (vhaddq, vhsubq, vmulhq)
	(vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
	* config/arm/arm_mve.h (vhsubq): Remove.
	(vhaddq): Remove.
	(vhaddq_m): Remove.
	(vhsubq_m): Remove.
	(vhaddq_x): Remove.
	(vhsubq_x): Remove.
	(vhsubq_u8): Remove.
	(vhsubq_n_u8): Remove.
	(vhaddq_u8): Remove.
	(vhaddq_n_u8): Remove.
	(vhsubq_s8): Remove.
	(vhsubq_n_s8): Remove.
	(vhaddq_s8): Remove.
	(vhaddq_n_s8): Remove.
	(vhsubq_u16): Remove.
	(vhsubq_n_u16): Remove.
	(vhaddq_u16): Remove.
	(vhaddq_n_u16): Remove.
	(vhsubq_s16): Remove.
	(vhsubq_n_s16): Remove.
	(vhaddq_s16): Remove.
	(vhaddq_n_s16): Remove.
	(vhsubq_u32): Remove.
	(vhsubq_n_u32): Remove.
	(vhaddq_u32): Remove.
	(vhaddq_n_u32): Remove.
	(vhsubq_s32): Remove.
	(vhsubq_n_s32): Remove.
	(vhaddq_s32): Remove.
	(vhaddq_n_s32): Remove.
	(vhaddq_m_n_s8): Remove.
	(vhaddq_m_n_s32): Remove.
	(vhaddq_m_n_s16): Remove.
	(vhaddq_m_n_u8): Remove.
	(vhaddq_m_n_u32): Remove.
	(vhaddq_m_n_u16): Remove.
	(vhaddq_m_s8): Remove.
	(vhaddq_m_s32): Remove.
	(vhaddq_m_s16): Remove.
	(vhaddq_m_u8): Remove.
	(vhaddq_m_u32): Remove.
	(vhaddq_m_u16): Remove.
	(vhsubq_m_n_s8): Remove.
	(vhsubq_m_n_s32): Remove.
	(vhsubq_m_n_s16): Remove.
	(vhsubq_m_n_u8): Remove.
	(vhsubq_m_n_u32): Remove.
	(vhsubq_m_n_u16): Remove.
	(vhsubq_m_s8): Remove.
	(vhsubq_m_s32): Remove.
	(vhsubq_m_s16): Remove.
	(vhsubq_m_u8): Remove.
	(vhsubq_m_u32): Remove.
	(vhsubq_m_u16): Remove.
	(vhaddq_x_n_s8): Remove.
	(vhaddq_x_n_s16): Remove.
	(vhaddq_x_n_s32): Remove.
	(vhaddq_x_n_u8): Remove.
	(vhaddq_x_n_u16): Remove.
	(vhaddq_x_n_u32): Remove.
	(vhaddq_x_s8): Remove.
	(vhaddq_x_s16): Remove.
	(vhaddq_x_s32): Remove.
	(vhaddq_x_u8): Remove.
	(vhaddq_x_u16): Remove.
	(vhaddq_x_u32): Remove.
	(vhsubq_x_n_s8): Remove.
	(vhsubq_x_n_s16): Remove.
	(vhsubq_x_n_s32): Remove.
	(vhsubq_x_n_u8): Remove.
	(vhsubq_x_n_u16): Remove.
	(vhsubq_x_n_u32): Remove.
	(vhsubq_x_s8): Remove.
	(vhsubq_x_s16): Remove.
	(vhsubq_x_s32): Remove.
	(vhsubq_x_u8): Remove.
	(vhsubq_x_u16): Remove.
	(vhsubq_x_u32): Remove.
	(__arm_vhsubq_u8): Remove.
	(__arm_vhsubq_n_u8): Remove.
	(__arm_vhaddq_u8): Remove.
	(__arm_vhaddq_n_u8): Remove.
	(__arm_vhsubq_s8): Remove.
	(__arm_vhsubq_n_s8): Remove.
	(__arm_vhaddq_s8): Remove.
	(__arm_vhaddq_n_s8): Remove.
	(__arm_vhsubq_u16): Remove.
	(__arm_vhsubq_n_u16): Remove.
	(__arm_vhaddq_u16): Remove.
	(__arm_vhaddq_n_u16): Remove.
	(__arm_vhsubq_s16): Remove.
	(__arm_vhsubq_n_s16): Remove.
	(__arm_vhaddq_s16): Remove.
	(__arm_vhaddq_n_s16): Remove.
	(__arm_vhsubq_u32): Remove.
	(__arm_vhsubq_n_u32): Remove.
	(__arm_vhaddq_u32): Remove.
	(__arm_vhaddq_n_u32): Remove.
	(__arm_vhsubq_s32): Remove.
	(__arm_vhsubq_n_s32): Remove.
	(__arm_vhaddq_s32): Remove.
	(__arm_vhaddq_n_s32): Remove.
	(__arm_vhaddq_m_n_s8): Remove.
	(__arm_vhaddq_m_n_s32): Remove.
	(__arm_vhaddq_m_n_s16): Remove.
	(__arm_vhaddq_m_n_u8): Remove.
	(__arm_vhaddq_m_n_u32): Remove.
	(__arm_vhaddq_m_n_u16): Remove.
	(__arm_vhaddq_m_s8): Remove.
	(__arm_vhaddq_m_s32): Remove.
	(__arm_vhaddq_m_s16): Remove.
	(__arm_vhaddq_m_u8): Remove.
	(__arm_vhaddq_m_u32): Remove.
	(__arm_vhaddq_m_u16): Remove.
	(__arm_vhsubq_m_n_s8): Remove.
	(__arm_vhsubq_m_n_s32): Remove.
	(__arm_vhsubq_m_n_s16): Remove.
	(__arm_vhsubq_m_n_u8): Remove.
	(__arm_vhsubq_m_n_u32): Remove.
	(__arm_vhsubq_m_n_u16): Remove.
	(__arm_vhsubq_m_s8): Remove.
	(__arm_vhsubq_m_s32): Remove.
	(__arm_vhsubq_m_s16): Remove.
	(__arm_vhsubq_m_u8): Remove.
	(__arm_vhsubq_m_u32): Remove.
	(__arm_vhsubq_m_u16): Remove.
	(__arm_vhaddq_x_n_s8): Remove.
	(__arm_vhaddq_x_n_s16): Remove.
	(__arm_vhaddq_x_n_s32): Remove.
	(__arm_vhaddq_x_n_u8): Remove.
	(__arm_vhaddq_x_n_u16): Remove.
	(__arm_vhaddq_x_n_u32): Remove.
	(__arm_vhaddq_x_s8): Remove.
	(__arm_vhaddq_x_s16): Remove.
	(__arm_vhaddq_x_s32): Remove.
	(__arm_vhaddq_x_u8): Remove.
	(__arm_vhaddq_x_u16): Remove.
	(__arm_vhaddq_x_u32): Remove.
	(__arm_vhsubq_x_n_s8): Remove.
	(__arm_vhsubq_x_n_s16): Remove.
	(__arm_vhsubq_x_n_s32): Remove.
	(__arm_vhsubq_x_n_u8): Remove.
	(__arm_vhsubq_x_n_u16): Remove.
	(__arm_vhsubq_x_n_u32): Remove.
	(__arm_vhsubq_x_s8): Remove.
	(__arm_vhsubq_x_s16): Remove.
	(__arm_vhsubq_x_s32): Remove.
	(__arm_vhsubq_x_u8): Remove.
	(__arm_vhsubq_x_u16): Remove.
	(__arm_vhsubq_x_u32): Remove.
	(__arm_vhsubq): Remove.
	(__arm_vhaddq): Remove.
	(__arm_vhaddq_m): Remove.
	(__arm_vhsubq_m): Remove.
	(__arm_vhaddq_x): Remove.
	(__arm_vhsubq_x): Remove.
	(vmulhq): Remove.
	(vmulhq_m): Remove.
	(vmulhq_x): Remove.
	(vmulhq_u8): Remove.
	(vmulhq_s8): Remove.
	(vmulhq_u16): Remove.
	(vmulhq_s16): Remove.
	(vmulhq_u32): Remove.
	(vmulhq_s32): Remove.
	(vmulhq_m_s8): Remove.
	(vmulhq_m_s32): Remove.
	(vmulhq_m_s16): Remove.
	(vmulhq_m_u8): Remove.
	(vmulhq_m_u32): Remove.
	(vmulhq_m_u16): Remove.
	(vmulhq_x_s8): Remove.
	(vmulhq_x_s16): Remove.
	(vmulhq_x_s32): Remove.
	(vmulhq_x_u8): Remove.
	(vmulhq_x_u16): Remove.
	(vmulhq_x_u32): Remove.
	(__arm_vmulhq_u8): Remove.
	(__arm_vmulhq_s8): Remove.
	(__arm_vmulhq_u16): Remove.
	(__arm_vmulhq_s16): Remove.
	(__arm_vmulhq_u32): Remove.
	(__arm_vmulhq_s32): Remove.
	(__arm_vmulhq_m_s8): Remove.
	(__arm_vmulhq_m_s32): Remove.
	(__arm_vmulhq_m_s16): Remove.
	(__arm_vmulhq_m_u8): Remove.
	(__arm_vmulhq_m_u32): Remove.
	(__arm_vmulhq_m_u16): Remove.
	(__arm_vmulhq_x_s8): Remove.
	(__arm_vmulhq_x_s16): Remove.
	(__arm_vmulhq_x_s32): Remove.
	(__arm_vmulhq_x_u8): Remove.
	(__arm_vmulhq_x_u16): Remove.
	(__arm_vmulhq_x_u32): Remove.
	(__arm_vmulhq): Remove.
	(__arm_vmulhq_m): Remove.
	(__arm_vmulhq_x): Remove.
	(vqsubq): Remove.
	(vqaddq): Remove.
	(vqaddq_m): Remove.
	(vqsubq_m): Remove.
	(vqsubq_u8): Remove.
	(vqsubq_n_u8): Remove.
	(vqaddq_u8): Remove.
	(vqaddq_n_u8): Remove.
	(vqsubq_s8): Remove.
	(vqsubq_n_s8): Remove.
	(vqaddq_s8): Remove.
	(vqaddq_n_s8): Remove.
	(vqsubq_u16): Remove.
	(vqsubq_n_u16): Remove.
	(vqaddq_u16): Remove.
	(vqaddq_n_u16): Remove.
	(vqsubq_s16): Remove.
	(vqsubq_n_s16): Remove.
	(vqaddq_s16): Remove.
	(vqaddq_n_s16): Remove.
	(vqsubq_u32): Remove.
	(vqsubq_n_u32): Remove.
	(vqaddq_u32): Remove.
	(vqaddq_n_u32): Remove.
	(vqsubq_s32): Remove.
	(vqsubq_n_s32): Remove.
	(vqaddq_s32): Remove.
	(vqaddq_n_s32): Remove.
	(vqaddq_m_n_s8): Remove.
	(vqaddq_m_n_s32): Remove.
	(vqaddq_m_n_s16): Remove.
	(vqaddq_m_n_u8): Remove.
	(vqaddq_m_n_u32): Remove.
	(vqaddq_m_n_u16): Remove.
	(vqaddq_m_s8): Remove.
	(vqaddq_m_s32): Remove.
	(vqaddq_m_s16): Remove.
	(vqaddq_m_u8): Remove.
	(vqaddq_m_u32): Remove.
	(vqaddq_m_u16): Remove.
	(vqsubq_m_n_s8): Remove.
	(vqsubq_m_n_s32): Remove.
	(vqsubq_m_n_s16): Remove.
	(vqsubq_m_n_u8): Remove.
	(vqsubq_m_n_u32): Remove.
	(vqsubq_m_n_u16): Remove.
	(vqsubq_m_s8): Remove.
	(vqsubq_m_s32): Remove.
	(vqsubq_m_s16): Remove.
	(vqsubq_m_u8): Remove.
	(vqsubq_m_u32): Remove.
	(vqsubq_m_u16): Remove.
	(__arm_vqsubq_u8): Remove.
	(__arm_vqsubq_n_u8): Remove.
	(__arm_vqaddq_u8): Remove.
	(__arm_vqaddq_n_u8): Remove.
	(__arm_vqsubq_s8): Remove.
	(__arm_vqsubq_n_s8): Remove.
	(__arm_vqaddq_s8): Remove.
	(__arm_vqaddq_n_s8): Remove.
	(__arm_vqsubq_u16): Remove.
	(__arm_vqsubq_n_u16): Remove.
	(__arm_vqaddq_u16): Remove.
	(__arm_vqaddq_n_u16): Remove.
	(__arm_vqsubq_s16): Remove.
	(__arm_vqsubq_n_s16): Remove.
	(__arm_vqaddq_s16): Remove.
	(__arm_vqaddq_n_s16): Remove.
	(__arm_vqsubq_u32): Remove.
	(__arm_vqsubq_n_u32): Remove.
	(__arm_vqaddq_u32): Remove.
	(__arm_vqaddq_n_u32): Remove.
	(__arm_vqsubq_s32): Remove.
	(__arm_vqsubq_n_s32): Remove.
	(__arm_vqaddq_s32): Remove.
	(__arm_vqaddq_n_s32): Remove.
	(__arm_vqaddq_m_n_s8): Remove.
	(__arm_vqaddq_m_n_s32): Remove.
	(__arm_vqaddq_m_n_s16): Remove.
	(__arm_vqaddq_m_n_u8): Remove.
	(__arm_vqaddq_m_n_u32): Remove.
	(__arm_vqaddq_m_n_u16): Remove.
	(__arm_vqaddq_m_s8): Remove.
	(__arm_vqaddq_m_s32): Remove.
	(__arm_vqaddq_m_s16): Remove.
	(__arm_vqaddq_m_u8): Remove.
	(__arm_vqaddq_m_u32): Remove.
	(__arm_vqaddq_m_u16): Remove.
	(__arm_vqsubq_m_n_s8): Remove.
	(__arm_vqsubq_m_n_s32): Remove.
	(__arm_vqsubq_m_n_s16): Remove.
	(__arm_vqsubq_m_n_u8): Remove.
	(__arm_vqsubq_m_n_u32): Remove.
	(__arm_vqsubq_m_n_u16): Remove.
	(__arm_vqsubq_m_s8): Remove.
	(__arm_vqsubq_m_s32): Remove.
	(__arm_vqsubq_m_s16): Remove.
	(__arm_vqsubq_m_u8): Remove.
	(__arm_vqsubq_m_u32): Remove.
	(__arm_vqsubq_m_u16): Remove.
	(__arm_vqsubq): Remove.
	(__arm_vqaddq): Remove.
	(__arm_vqaddq_m): Remove.
	(__arm_vqsubq_m): Remove.
	(vqdmulhq): Remove.
	(vqdmulhq_m): Remove.
	(vqdmulhq_s8): Remove.
	(vqdmulhq_n_s8): Remove.
	(vqdmulhq_s16): Remove.
	(vqdmulhq_n_s16): Remove.
	(vqdmulhq_s32): Remove.
	(vqdmulhq_n_s32): Remove.
	(vqdmulhq_m_n_s8): Remove.
	(vqdmulhq_m_n_s32): Remove.
	(vqdmulhq_m_n_s16): Remove.
	(vqdmulhq_m_s8): Remove.
	(vqdmulhq_m_s32): Remove.
	(vqdmulhq_m_s16): Remove.
	(__arm_vqdmulhq_s8): Remove.
	(__arm_vqdmulhq_n_s8): Remove.
	(__arm_vqdmulhq_s16): Remove.
	(__arm_vqdmulhq_n_s16): Remove.
	(__arm_vqdmulhq_s32): Remove.
	(__arm_vqdmulhq_n_s32): Remove.
	(__arm_vqdmulhq_m_n_s8): Remove.
	(__arm_vqdmulhq_m_n_s32): Remove.
	(__arm_vqdmulhq_m_n_s16): Remove.
	(__arm_vqdmulhq_m_s8): Remove.
	(__arm_vqdmulhq_m_s32): Remove.
	(__arm_vqdmulhq_m_s16): Remove.
	(__arm_vqdmulhq): Remove.
	(__arm_vqdmulhq_m): Remove.
	(vrhaddq): Remove.
	(vrhaddq_m): Remove.
	(vrhaddq_x): Remove.
	(vrhaddq_u8): Remove.
	(vrhaddq_s8): Remove.
	(vrhaddq_u16): Remove.
	(vrhaddq_s16): Remove.
	(vrhaddq_u32): Remove.
	(vrhaddq_s32): Remove.
	(vrhaddq_m_s8): Remove.
	(vrhaddq_m_s32): Remove.
	(vrhaddq_m_s16): Remove.
	(vrhaddq_m_u8): Remove.
	(vrhaddq_m_u32): Remove.
	(vrhaddq_m_u16): Remove.
	(vrhaddq_x_s8): Remove.
	(vrhaddq_x_s16): Remove.
	(vrhaddq_x_s32): Remove.
	(vrhaddq_x_u8): Remove.
	(vrhaddq_x_u16): Remove.
	(vrhaddq_x_u32): Remove.
	(__arm_vrhaddq_u8): Remove.
	(__arm_vrhaddq_s8): Remove.
	(__arm_vrhaddq_u16): Remove.
	(__arm_vrhaddq_s16): Remove.
	(__arm_vrhaddq_u32): Remove.
	(__arm_vrhaddq_s32): Remove.
	(__arm_vrhaddq_m_s8): Remove.
	(__arm_vrhaddq_m_s32): Remove.
	(__arm_vrhaddq_m_s16): Remove.
	(__arm_vrhaddq_m_u8): Remove.
	(__arm_vrhaddq_m_u32): Remove.
	(__arm_vrhaddq_m_u16): Remove.
	(__arm_vrhaddq_x_s8): Remove.
	(__arm_vrhaddq_x_s16): Remove.
	(__arm_vrhaddq_x_s32): Remove.
	(__arm_vrhaddq_x_u8): Remove.
	(__arm_vrhaddq_x_u16): Remove.
	(__arm_vrhaddq_x_u32): Remove.
	(__arm_vrhaddq): Remove.
	(__arm_vrhaddq_m): Remove.
	(__arm_vrhaddq_x): Remove.
	(vrmulhq): Remove.
	(vrmulhq_m): Remove.
	(vrmulhq_x): Remove.
	(vrmulhq_u8): Remove.
	(vrmulhq_s8): Remove.
	(vrmulhq_u16): Remove.
	(vrmulhq_s16): Remove.
	(vrmulhq_u32): Remove.
	(vrmulhq_s32): Remove.
	(vrmulhq_m_s8): Remove.
	(vrmulhq_m_s32): Remove.
	(vrmulhq_m_s16): Remove.
	(vrmulhq_m_u8): Remove.
	(vrmulhq_m_u32): Remove.
	(vrmulhq_m_u16): Remove.
	(vrmulhq_x_s8): Remove.
	(vrmulhq_x_s16): Remove.
	(vrmulhq_x_s32): Remove.
	(vrmulhq_x_u8): Remove.
	(vrmulhq_x_u16): Remove.
	(vrmulhq_x_u32): Remove.
	(__arm_vrmulhq_u8): Remove.
	(__arm_vrmulhq_s8): Remove.
	(__arm_vrmulhq_u16): Remove.
	(__arm_vrmulhq_s16): Remove.
	(__arm_vrmulhq_u32): Remove.
	(__arm_vrmulhq_s32): Remove.
	(__arm_vrmulhq_m_s8): Remove.
	(__arm_vrmulhq_m_s32): Remove.
	(__arm_vrmulhq_m_s16): Remove.
	(__arm_vrmulhq_m_u8): Remove.
	(__arm_vrmulhq_m_u32): Remove.
	(__arm_vrmulhq_m_u16): Remove.
	(__arm_vrmulhq_x_s8): Remove.
	(__arm_vrmulhq_x_s16): Remove.
	(__arm_vrmulhq_x_s32): Remove.
	(__arm_vrmulhq_x_u8): Remove.
	(__arm_vrmulhq_x_u16): Remove.
	(__arm_vrmulhq_x_u32): Remove.
	(__arm_vrmulhq): Remove.
	(__arm_vrmulhq_m): Remove.
	(__arm_vrmulhq_x): Remove.

Factorize vabdq, vhaddq, vhsubq, vmulhq, vqaddq_u, vqdmulhq,
vqrdmulhq, vqrshlq, vqshlq, vqsubq_u, vrhaddq, vrmulhq, vrshlq
so that they use the same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_INT_SU_BINARY): New.
	(mve_insn): Add vabdq, vhaddq, vhsubq, vmulhq, vqaddq, vqdmulhq,
	vqrdmulhq, vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq.
	(supf): Add VQDMULHQ_S, VQRDMULHQ_S.
	* config/arm/mve.md (mve_vabdq_<supf><mode>)
	(@mve_vhaddq_<supf><mode>, mve_vhsubq_<supf><mode>)
	(mve_vmulhq_<supf><mode>, mve_vqaddq_<supf><mode>)
	(mve_vqdmulhq_s<mode>, mve_vqrdmulhq_s<mode>)
	(mve_vqrshlq_<supf><mode>, mve_vqshlq_<supf><mode>)
	(mve_vqsubq_<supf><mode>, @mve_vrhaddq_<supf><mode>)
	(mve_vrmulhq_<supf><mode>, mve_vrshlq_<supf><mode>): Merge into
	...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	* config/arm/vec-common.md (avg<mode>3_floor, uavg<mode>3_floor)
	(avg<mode>3_ceil, uavg<mode>3_ceil): Use gen_mve_q instead of
	gen_mve_vhaddq / gen_mve_vrhaddq.