This also works with Emacs 30 Tree-Sitter C and C++ modes, as they are
submodes.

ChangeLog:

	* .dir-locals.el: Change c-mode to a list of C, C++ and ObjC
	modes that Emacs currently provides.

More enable-rtl-checking fixes for ext-dce.  Very similar to the one recently
posted, this time covering more of the shift ops.

I checked all instances of CONSTANT_P guarding [U]INTVAL and fixed all that
looked wrong.  I also created a dummy assembler/linker so that I could run the
GCC testsuite on gcn and verified that wasn't tripping any rtl-checking bugs in
ext-dce anymore.

Obviously this has also gone through x86 bootstrap and regression tested.

Pushing to the trunk.

	pr target/116104
gcc/
	* ext-dce.cc (carry_backpropagate): Change more guards of [U]INTVAL to
	test CONST_INT_P rather than CONSTANT_P, fixing rtl-checking failures.

Loading an arbitrary constant address in a register is expensive for
PRU.  So enable section anchoring by default to utilize the unsigned
byte constant offset operand of load/store instructions.

gcc/ChangeLog:

	* common/config/pru/pru-common.cc
	(TARGET_OPTION_OPTIMIZATION_TABLE): New definition.
	* config/pru/pru.cc (TARGET_MIN_ANCHOR_OFFSET): Set minimal
	anchor offset.
	(TARGET_MAX_ANCHOR_OFFSET): Set maximum anchor offset.

gcc/testsuite/ChangeLog:

	* gcc.target/pru/section-anchors-1.c: New test.
	* gcc.target/pru/section-anchors-2.c: New test.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

PRU and other simulator targets do not pass any argv arguments
to main.  Instead of erroneously relying on argc==0, use a volatile
variable instead.

I reverted the fix for PR67947 in r6-3891-g8a18fcf4aa1d5c, and made sure
that the updated test case still fails for x86_64:

  $ make check-gcc-c RUNTESTFLAGS="dg-torture.exp=pr67947.c"
  ...
  FAIL: gcc.dg/torture/pr67947.c   -O1  execution test
  ...
  # of expected passes            8
  # of unexpected failures        8

Fix was suggested by Andrew Pinski in PR116154.  Committed as obvious.

	PR testsuite/116154

gcc/testsuite/ChangeLog:

	* gcc.dg/torture/pr67947.c: Use volatile variable instead of
	argc.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

We already have a valid 'dg-do run' (- vs _) directive, so drop the bogus
one.

libstdc++-v3/ChangeLog:
	* testsuite/28_regex/traits/char/translate.cc: Drop bogus 'dg_do run'.

This fixes a testsuite regression seen on m68k after some of the recent ext-dce
changes.  Ultimately Richard S and I have concluded the bug was a latent issue
in subreg simplification.

Essentially when simplifying something like

(set (target:M1) (subreg:M1 (subreg:M2 (reg:M1) 0) 0))

Where M1 > M2.  We'd simplify to:

(set (target:M1) (reg:M1))

The problem is on a big endian target that's wrong.   Consider if M1 is DI and
M2 is SI.    The original should extract bits 32..63 from the source register
and store them into bits 0..31 of the target register. In the simplified form
it's just a copy, so bits 0..63 of the source end up bits 0..63 of the target.

This shows up as the following regressions on the m68k:

> Tests that now fail, but worked before (3 tests):
>
> gcc: gcc.c-torture/execute/960416-1.c   -O2  execution test
> gcc: gcc.c-torture/execute/960416-1.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none  execution test
> gcc: gcc.c-torture/execute/960416-1.c   -Os  execution test

The fix is pretty trivial, instead of hardcoding "0" as the byte offset in the
test for the simplification, instead we need to use the subreg_lowpart_offset.

Anyway, bootstrapped and regression tested on m68k and x86_64 and tested on the
other embedded targets as well without regressions.  Naturally it fixes the
regression noted above.  I haven't see other testsuite improvements when I spot
checked some of the big endian crosses.

	PR rtl-optimization/116136
gcc/
	* simplify-rtx.cc (simplify_context::simplify_subreg): Check
	that we're working with the lowpart offset rather than byte 0.

The linux man page for strerror says that some systems return NULL for
an unknown error number. That violates the C and POSIX standards, but we
can esily handle it to avoid a segfault.

libstdc++-v3/ChangeLog:

	* src/c++11/system_error.cc (strerror_string): Handle
	non-conforming NULL return from strerror.

The testsuite automatically appends "@euro" to "xx.ISO8859-15" locale
names on all targets except FreeBSD, DragonflyBSD, and NetBSD. It should
only be for Glibc, not all non-BSD targets.

libstdc++-v3/ChangeLog:

	* testsuite/lib/libstdc++.exp (check_v3_target_namedlocale):
	Only append "@euro" to ".ISO8859-15" locales for Glibc.

We already supported this feature, but couldn't set the feature test
macro accordingly because we were missing support for older features.
Now that we support all the older <format> changes, we can set this to
the correct value.

libstdc++-v3/ChangeLog:

	* include/bits/version.def (format): Update value for C++26.
	* include/bits/version.h: Regenerate.
	* include/std/format (runtime_format, wruntime_format): Check
	__cpp_lib_format instead of __cplusplus.
	* testsuite/std/format/functions/format.cc: Update expected
	value of macro for C++26 mode.

Implement the std::format changes from P2637R3. This adds visit member
functions to std::basic_format_arg and deprecates the non-member
function std::visit_format_arg.

libstdc++-v3/ChangeLog:

	PR libstdc++/110356
	* include/bits/c++config (_GLIBCXX26_DEPRECATED): Define.
	(_GLIBCXX26_DEPRECATED_SUGGEST): Define.
	* include/bits/version.def (format): Update for C++26.
	* include/bits/version.h: Regenerate.
	* include/std/format (basic_format_arg::visit): New member
	functions.
	(visit_format_arg): Add deprecated attribute.
	* testsuite/std/format/arguments/args.cc: Expect deprecated
	warnings. Check member visit.
	* testsuite/std/format/functions/format.cc: Update expected
	value for __cpp_lib_format macro.
	* testsuite/std/format/parse_ctx.cc: Add dg-warning for
	deprecation.

Implement the std::variant changes from P2637R3.

libstdc++-v3/ChangeLog:

	PR libstdc++/110356
	* include/bits/version.def (variant): Update for C++26.
	* include/bits/version.h: Regenerate.
	* include/std/variant (variant::visit): New member functions.
	* testsuite/20_util/variant/visit.cc: Check second alternative.
	* testsuite/20_util/variant/visit_member.cc: New test.

Implement the changes from P2757R3, which enhance the parse context to
be able to do type checking on format arguments, and to use that to
ensure that args used for width and precisions are integral types.

libstdc++-v3/ChangeLog:

	PR libstdc++/115776
	* include/bits/version.def (format): Update for C++26.
	* include/bits/version.h: Regenerate.
	* include/std/format (basic_format_parse_context): Remove
	default argument from constructor and split into two
	constructors. Make the constructor taking size_t private for
	C++26 and later.
	(basic_format_parse_context::check_dynamic_spec): New member
	function template.
	(basic_format_parse_context::check_dynamic_spec_integral): New
	member function.
	(basic_format_parse_context::check_dynamic_spec_string):
	Likewise.
	(__format::_Spec::_S_parse_width_or_precision): Use
	check_dynamic_spec_integral.
	(__format::__to_arg_t_enum): New helper function.
	(basic_format_arg):  Declare __to_arg_t_enum as friend.
	(__format::_Scanner): Define and use a derived parse context
	type.
	(__format::_Checking_scanner): Make arg types available to parse
	context.
	* testsuite/std/format/functions/format.cc: Check for new values
	of __cpp_lib_format macro.
	* testsuite/std/format/parse_ctx.cc: Check all members of
	basic_format_parse_context.
	* testsuite/std/format/parse_ctx_neg.cc: New test.
	* testsuite/std/format/string.cc: Add more checks for dynamic
	width and precision args.

We already enable this for -std=gnu++20 but we can do it for -std=c++20
too. Both libc++ and MSVC also treat this change as a DR for C++20.

Now that the previous change to the value of __cpp_lib_format is
supported, we can finally update it to 202304 to indicate support for
this feature too.

libstdc++-v3/ChangeLog:

	* include/bits/version.def (format): Update value for P2510R3.
	* include/bits/version.h: Regenerate.
	* include/std/format (_GLIBCXX_P2518R3): Remove misspelled macro
	and check __glibcxx_format instead.
	* testsuite/std/format/functions/format.cc: Check value of the
	__cpp_lib_format macro for formatting pointers support.
	* testsuite/std/format/parse_ctx.cc: Likewise.

This implements the C++23 paper P2419R2 (Clarify handling of encodings
in localized formatting of chrono types). The requirement is that when
the literal encoding is "a Unicode encoding form" and the formatting
locale uses a different encoding, any locale-specific strings such as
"août" for std::chrono::August should be converted to the literal
encoding.

Using the recently-added std::locale::encoding() function we can check
the locale's encoding and then use iconv if a conversion is needed.
Because nl_langinfo_l and iconv_open both allocate memory, a naive
implementation would perform multiple allocations and deallocations for
every snippet of locale-specific text that needs to be converted to
UTF-8. To avoid that, a new internal locale::facet is defined to store
the text_encoding and an iconv_t descriptor, which are then cached in
the formatting locale. This requires access to the internals of a
std::locale object in src/c++20/format.cc, so that new file needs to be
compiled with -fno-access-control, as well as -std=gnu++26 in order to
use std::text_encoding.

Because the new std::text_encoding and std::locale::encoding() symbols
are only in the libstdc++exp.a archive, we need to include
src/c++26/text_encoding.cc in the main library, but not export its
symbols yet. This means they can be used by the two new functions which
are exported from the main library.

The encoding conversions are done for C++20, treating it as a DR that
resolves LWG 3656.

With this change we can increase the value of the __cpp_lib_format macro
for C++23. The value should be 202207 for P2419R2, but we already
implement P2510R3 (Formatting pointers) so can use the value 202304.

libstdc++-v3/ChangeLog:

	PR libstdc++/109162
	* acinclude.m4 (libtool_VERSION): Update to 6:34:0.
	* config/abi/pre/gnu.ver: Disambiguate old patters. Add new
	GLIBCXX_3.4.34 symbol version and new exports.
	* configure: Regenerate.
	* include/bits/chrono_io.h (_ChronoSpec::_M_locale_specific):
	Add new accessor functions to use a reserved bit in _Spec.
	(__formatter_chrono::_M_parse): Use _M_locale_specific(true)
	when chrono-specs contains locale-dependent conversion
	specifiers.
	(__formatter_chrono::_M_format): Open iconv descriptor if
	conversion to UTF-8 will be needed.
	(__formatter_chrono::_M_write): New function to write a
	localized string with possible character conversion.
	(__formatter_chrono::_M_a_A, __formatter_chrono::_M_b_B)
	(__formatter_chrono::_M_p, __formatter_chrono::_M_r)
	(__formatter_chrono::_M_x, __formatter_chrono::_M_X)
	(__formatter_chrono::_M_locale_fmt): Use _M_write.
	* include/bits/version.def (format): Update value.
	* include/bits/version.h: Regenerate.
	* include/std/format (_GLIBCXX_P2518R3): Check feature test
	macro instead of __cplusplus.
	(basic_format_context): Declare __formatter_chrono as friend.
	* src/c++20/Makefile.am: Add new file.
	* src/c++20/Makefile.in: Regenerate.
	* src/c++20/format.cc: New file.
	* testsuite/std/time/format_localized.cc: New test.
	* testsuite/util/testsuite_abi.cc: Add new symbol version.

Per gccint, 'dg-require-*' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.

	* gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c: Fix dg-require-profiling
	directive order.
	* gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c: Likewise.

Per gccint, 'dg-require-effective-target' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.

gcc/testsuite/ChangeLog:
	* gcc.target/aarch64/aapcs64/func-ret-3.c: Fix dg-require-effective-target directive order.
	* gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise.
	* gfortran.dg/PR100914.f90: Likewise.

libgomp/ChangeLog:
	* testsuite/libgomp.c++/pr24455.C: Fix dg-require-effective-target directive order.
	* testsuite/libgomp.c/pr24455.c: Likewise.

We want 'dg-do preprocess', not 'dg-do-preprocess'. Fix that.

	PR target/106828
	* g++.target/loongarch/pr106828.C: Fix 'dg-do compile' typo.

We want 'dg-do compile', not 'dg-do-compile'. Fix that.

	PR target/69194
	PR c++/92024
	PR c++/110057
	* c-c++-common/Wshadow-1.c: Fix 'dg-do compile' typo.
	* g++.dg/tree-ssa/devirt-array-destructor-1.C: Likewise.
	* g++.dg/tree-ssa/devirt-array-destructor-2.C: Likewise.
	* gcc.target/arm/pr69194.c: Likewise.

'dg-run' is not a valid dejagnu directive, 'dg-do run' is needed here
for the test to be executed.

That said, it actually seems to be executed for me anyway, presumably
a default in the directory, but let's fix it to be consistent with
other uses in the tree and in that test directory even.

libgomp/ChangeLog:
	* testsuite/libgomp.c++/declare-target-indirect-1.C: Fix 'dg-run' typo.

The ACLE declares several helper types and functions to facilitate construction
of `fpm` arguments. These are available when one of the arm_neon.h, arm_sve.h,
or arm_sme.h headers is included. These helpers don't map to specific FP8
instructions and there's no expectation that they will produce a given code
sequence, they're just an abstraction and an aid to the programmer. Thus they are
implemented in a new header file arm_private_fp8.h
Users are not expected to include this file, as it is a mere implementation detail,
subject to change. A check is included to guard against direct inclusion.

gcc/ChangeLog:

	* config.gcc (extra_headers): Install arm_private_fp8.h.
	* config/aarch64/arm_neon.h: Include arm_private_fp8.h.
	* config/aarch64/arm_sve.h: Likewise.
	* config/aarch64/arm_private_fp8.h: New file
	(fpm_t): New type representing fpmr values.
	(enum __ARM_FPM_FORMAT): New enum representing valid fp8 formats.
	(enum __ARM_FPM_OVERFLOW): New enum representing how some fp8
	calculations work.
	(__arm_fpm_init): New.
	(__arm_set_fpm_src1_format): Likewise.
	(__arm_set_fpm_src2_format): Likewise.
	(__arm_set_fpm_dst_format): Likewise.
	(__arm_set_fpm_overflow_cvt): Likewise.
	(__arm_set_fpm_overflow_mul): Likewise.
	(__arm_set_fpm_lscale): Likewise.
	(__arm_set_fpm_lscale2): Likewise.
	(__arm_set_fpm_nscale): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/fp8-helpers-neon.c: New test of fpmr helper
	functions.
	* gcc.target/aarch64/acle/fp8-helpers-sve.c: New test of fpmr helper
	functions presence.
	* gcc.target/aarch64/acle/fp8-helpers-sme.c: New test of fpmr helper
	functions presence.

Unlike most system registers, fpmr can be heavily written to in code that
exercises the fp8 functionality. That is because every fp8 instrinsic call
can potentially change the value of fpmr.
Rather than just use an unspec, we treat the fpmr system register like
all other registers and use a move operation to read and write to it.

We introduce a new class of moveable system registers that, currently,
only accepts fpmr and a new constraint, Umv, that allows us to
selectively use mrs and msr instructions when expanding rtl for them.
Given that there is code that depends on "real" registers coming before
"fake" ones, we introduce a new constant FPM_REGNUM that uses an
existing value and renumber registers below that.
This requires us to update the bitmaps that describe which registers
belong to each register class.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_hard_regno_nregs): Add
	support for MOVEABLE_SYSREGS class.
	(aarch64_hard_regno_mode_ok): Allow reads and writes to fpmr.
	(aarch64_regno_regclass): Support MOVEABLE_SYSREGS class.
	(aarch64_class_max_nregs): Likewise.
	* config/aarch64/aarch64.h (FIXED_REGISTERS): add fpmr.
	(CALL_REALLY_USED_REGISTERS): Likewise.
	(REGISTER_NAMES): Likewise.
	(enum reg_class): Add MOVEABLE_SYSREGS class.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Update class bitmaps to deal with fpmr,
	the new MOVEABLE_REGS class and renumbering of registers.
	* config/aarch64/aarch64.md: (FPM_REGNUM): added new register
	number, reusing old value.
	(FFR_REGNUM): Renumber.
	(FFRT_REGNUM): Likewise.
	(LOWERING_REGNUM): Likewise.
	(TPIDR2_BLOCK_REGNUM): Likewise.
	(SME_STATE_REGNUM): Likewise.
	(TPIDR2_SETUP_REGNUM): Likewise.
	(ZA_FREE_REGNUM): Likewise.
	(ZA_SAVED_REGNUM): Likewise.
	(ZA_REGNUM): Likewise.
	(ZT0_REGNUM): Likewise.
	(*mov<mode>_aarch64): Add support for moveable sysregs.
	(*movsi_aarch64): Likewise.
	(*movdi_aarch64): Likewise.
	* config/aarch64/constraints.md (MOVEABLE_SYSREGS): New constraint.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/fp8.c: New tests.

This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently.

gcc/ChangeLog:

	* config/aarch64/aarch64-option-extensions.def (fp8): New.
	* config/aarch64/aarch64.h (TARGET_FP8): Likewise.
	* doc/invoke.texi (AArch64 Options): Document new -march flags
	and extensions.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/fp8.c: New test.

Unfortunately, my r15-1946 fix broke the attached testcase; the
constexpr evaluation reported an error about not being able to
evaluate the code emitted by build_vec_init.  Jason figured out
it's because we were wrongly setting try_const to false, where
in fact it should have been true.  Value-initialization of scalars
is constexpr, so we should check that alongside of
type_has_constexpr_default_constructor.

	PR c++/115645

gcc/cp/ChangeLog:

	* init.cc (build_vec_init): When initializing a scalar type, try to
	create a constant initializer.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/constexpr-new23.C: New test.

32bit x86 CPUs won't natively support the FFS operation on a 64 bit
type.  Therefore, I'm setting the long long int part of the
switch-exp-transform-3.c test to only execute with 64bit targets.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/switch-exp-transform-3.c: Set the long long
	int test to only execute with 64bit targets.

Signed-off-by: Filip Kastl <fkastl@suse.cz>

Per a gcc-help thread we are generating sub-optimal code for
__builtin_bswap{32,64}.  To fix it:

- Use a single revb.d instruction for bswapdi2.
- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
  revb.2h + rotri.w for !TARGET_64BIT.
- Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single
  revb.2w instruction for bswapdi2 (x) r>> 32.

Unfortunately I cannot figure out a way to make the compiler generate
revb.4h or revh.{2w,d} instructions.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H,
	UNSPEC_REVH_D): Remove UNSPECs.
	(revb_4h, revh_d): Remove define_insn.
	(revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of
	an UNSPEC.
	(revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn.
	(bswapsi2): Change to define_expand.  Only expand to revb.2h +
	rotri.w if !TARGET_64BIT.
	(bswapdi2): Change to define_insn of which the output is just a
	revb.d instruction.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/revb.c: New test.

In r15-1207 I was too stupid to realize we just need to relax
ins_zero_bitmask_operand to allow using bstrins for aligning, instead of
adding a new split.  And, "> 12" in ins_zero_bitmask_operand also makes
no sense: it rejects bstrins for things like "x & ~4l" with no good
reason.

So fix my errors now.

gcc/ChangeLog:

	* config/loongarch/predicates.md (ins_zero_bitmask_operand):
	Cover more cases that bstrins can benefit.
	(high_bitmask_operand): Remove.
	* config/loongarch/constraints.md (Yy): Remove.
	* config/loongarch/loongarch.md (and<mode>3_align): Remove.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/bstrins-4.c: New test.

When we gimplify &MEM[0B + 4] we are re-folding the address in case
types are not canonical which ends up with a constant address that
recompute_tree_invariant_for_addr_expr ICEs on.  Properly guard
that call.

	PR middle-end/101478
	* gimplify.cc (gimplify_addr_expr): Check we still have an
	ADDR_EXPR before calling recompute_tree_invariant_for_addr_expr.

	* gcc.dg/pr101478.c: New testcase.

When introducing munroll-only-small-loops, the option was marked as
Target Save and added to -O2 default which makes attribute(optimize)
resets target option and causing error when cmdline has O1 and
funciton attribute has O2 and other target options. Mark this option
as Optimization to fix.

gcc/ChangeLog

	PR target/116065
	* config/i386/i386.opt (munroll-only-small-loops): Mark as
	Optimization instead of Save.

gcc/testsuite/ChangeLog

	PR target/116065
	* gcc.target/i386/pr116065.c: New test.

In g:9d20529d, I'd extended
insn_propagation to handle simple cases of hard-reg mode punning.
The punned "to" value was created using simplify_subreg rather
than simplify_gen_subreg, on the basis that hard-coded subregs
aren't generally useful after RA (where hard-reg propagation is
expected to happen).

This PR is about a case where the subreg gets pushed into the
operands of a plus, but the subreg on one of the operands
cannot be simplified.  Specifically, we have to generate
(subreg:SI (reg:DI sp) 0) rather than (reg:SI sp), since all
references to the stack pointer must be via stack_pointer_rtx.

However, code in x86 (reasonably) expects no subregs of registers
to appear after RA, except for special cases like strict_low_part.
This leads to an awkward situation where we can't ban subregs of sp
(because of the strict_low_part use), can't allow direct references
to sp in other modes (because of the stack_pointer_rtx requirement),
and can't allow rvalue uses of the subreg (because of the "no subregs
after RA" assumption).  It all seems a bit of a mess...

I sat on this for a while in the hope that a clean solution might
become apparent, but in the end, I think we'll just have to check
manually for nested subregs and punt on them.

gcc/
	PR rtl-optimization/115881
	* recog.cc: Include rtl-iter.h.
	(insn_propagation::apply_to_rvalue_1): Check that the result
	of simplify_subreg does not include nested subregs.

gcc/testsuite/
	PR rtl-optimization/115881
	* gcc.c-torture/compile/pr115881.c: New test.

As PR105359 shows, we disable some FLOAT128 expanders for
64-bit long double, but in fact IEEE float128 types like
__ieee128 are only guarded with TARGET_FLOAT128_TYPE and
TARGET_LONG_DOUBLE_128 is only checked when determining if
we can reuse long_double_type_node.  So this patch is to
relax all affected FLOAT128 expander conditions for
FLOAT128_IEEE_P.  By the way, currently IBM double double
type __ibm128 is guarded by TARGET_LONG_DOUBLE_128, so we
have to use TARGET_LONG_DOUBLE_128 for it.  IMHO, it's not
necessary and can be enhanced later.

Btw, for all test cases mentioned in PR105359, I removed
the xfails and tested them with explicit -mlong-double-64,
both pr79004.c and float128-hw.c are tested well and
float128-hw4.c isn't tested (unsupported due to 64 bit
long double conflicts with -mabi=ieeelongdouble).

	PR target/105359

gcc/ChangeLog:

	* config/rs6000/rs6000.md (@extenddf<FLOAT128:mode>2): Don't check
	TARGET_LONG_DOUBLE_128 for FLOAT128_IEEE_P modes.
	(extendsf<FLOAT128:mode>2): Likewise.
	(trunc<FLOAT128:mode>df2): Likewise.
	(trunc<FLOAT128:mode>sf2): Likewise.
	(floatsi<FLOAT128:mode>2): Likewise.
	(fix_trunc<FLOAT128:mode>si2): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr79004.c: Remove xfails.

r14-1832 adds recognition pattern, ifn and optab for ABD
(ABsolute Difference), we have some vector absolute
difference unsigned instructions since ISA 3.0, as the
associated test cases shown, they are not exploited well
as we don't define it (them) with a standard name.  So this
patch is to rename it with standard name first.  And it
merges both define_expand and define_insn as a separated
define_expand isn't needed.  Besides, it adjusts the RTL
pattern by using generic umax and umin rather than
UNSPEC_VADU, it's more meaningful and can catch umin/umax
opportunity.

gcc/ChangeLog:

	* config/rs6000/altivec.md (p9_vadu<mode>3): Rename to ...
	(uabd<mode>3): ... this.  Update RTL pattern with umin and umax rather
	than UNSPEC_VADU.
	(vadu<mode>3): Remove.
	(UNSPEC_VADU): Remove.
	(usadv16qi): Replace gen_p9_vaduv16qi3 with gen_uabdv16qi3.
	(usadv8hi): Replace gen_p9_vaduv8hi3 with gen_uabdv8hi3.
	* config/rs6000/rs6000-builtins.def (__builtin_altivec_vadub): Replace
	expander with uabdv16qi3.
	(__builtin_altivec_vaduh): Adjust expander with uabdv8hi3.
	(__builtin_altivec_vaduw): Adjust expander with uabdv4si3.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/abd-vectorize-1.c: New test.
	* gcc.target/powerpc/abd-vectorize-2.c: New test.

We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions.  But this
does not always work: for cases like x << 1 | y, the compiler
tends to do

    (sign_extend:DI
      (ior:SI (ashift:SI (reg:SI $r4)
                         (const_int 1))
              (reg:SI $r5)))

instead of

    (ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1)))
            (sign_extend:DI (reg:SI $r5)))

So we cannot match the ashlsi3_extend instruction here and we get:

    slli.w $r4,$r4,1
    or     $r4,$r5,$r4
    slli.w $r4,$r4,0    # <= redundant
    jr	   $r1

To eliminate this redundant extension we need to turn SImode shift etc.
to DImode "si3_extend" operations earlier, when we expand the SImode
operation.  We are already doing this for addition, now do it for
shifts, rotates, substract, multiplication, division, and modulo as
well.

The bytepick.w definition for TARGET_64BIT needs to be adjusted so it
won't be undone by the shift expanding.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (optab): Add (rotatert "rotr").
	(<optab:any_shift><mode>3, <optab:any_div><mode>3,
	sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name
	so we can redefine the names with define_expand.
	(*<optab:any_shift>si3_extend): Remove "*" so we can use them
	in expanders.
	(*subsi3_extended, *mulsi3_extended): Likewise, also remove the
	trailing "ed" for consistency.
	(*<optab:any_div>si3_extended): Add mode for sign_extend to
	prevent an ICE using it in expanders.
	(shift_w, arith_w): New define_code_iterator.
	(<optab:any_w><mode>3): New define_expand.  Expand with
	<optab:any_w>si3_extend for SImode if TARGET_64BIT.
	(<optab:arith_w><mode>3): Likewise.
	(mul<mode>3): Expand to mulsi3_extended for SImode if
	TARGET_64BIT and ISA_HAS_DIV32.
	(<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended
	for SImode if TARGET_64BIT.
	(rotl<mode>3): Expand to rotrsi3_extend for SImode if
	TARGET_64BIT.
	(bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift.
	(bitsize, bytepick_imm, bytepick_w_ashift_amount): New
	define_mode_attr.
	(bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change
	caused by 32-bit shift expanding.  Now bytepick_imm only covers
	2 and 3, separate one remaining case to ...
	(bytepick_w_1_extend): ... here, new define_insn.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/bitwise_extend.c: New test.

This implements the proposed resolution of LWG 4124, so that
low-resolution chrono::zoned_time objects can be formatted. The
formatter for zoned_time<D, P> needs to account for get_local_time
returning local_time<common_type_t<D, seconds>> not local_time<D>.

libstdc++-v3/ChangeLog:

	* include/bits/chrono_io.h (__local_time_fmt_for): New alias
	template.
	(formatter<zoned_time<D, P>>): Use __local_time_fmt_for.
	* testsuite/std/time/zoned_time/io.cc: Check zoned_time<minutes>
	can be formatted.

When formatting a chrono::zoned_time with an empty chrono-specs, we were
only formatting its _M_time member, but the ostream insertion operator
uses the format "{:L%F %T %Z}" which includes the time zone
abbreviation. The %Z should also be used when formatting with an empty
chrono-specs.

This commit makes _M_format_to_ostream handle __local_time_fmt
specializations directly, rather than calling itself recursively to
format the _M_time member. We need to be able to customize the output of
_M_format_to_ostream for __local_time_fmt, because we use that type for
gps_time and tai_time as well as for zoned_time and __local_time_fmt.
When formatting gps_time and tai_time we don't want to include the time
zone abbreviation in the "{}" output, but for zoned_time we do want to.
We can reuse the __is_neg flag passed to _M_format_to_ostream (via
_M_format) to say that we want the time zone abbreviation.  Currently
the __is_neg flag is only used for duration specializations, so it's
available for __local_time_fmt to use.

In addition to fixing the zoned_time output to use %Z, this commit also
changes the __local_time_fmt output to use %Z. Previously it didn't use
it, just like zoned_time.  The standard doesn't actually say how to
format local-time-format-t for an empty chrono-specs, but this behaviour
seems sensible and is what I'm proposing as part of LWG 4124.

While testing this I noticed that some chrono types were not being
tested with empty chrono-specs, so this adds more tests. I also noticed
that std/time/clock/local/io.cc was testing tai_time instead of
local_time, which was completely wrong. That's fixed now too.

libstdc++-v3/ChangeLog:

	* include/bits/chrono_io.h (__local_fmt_t): Remove unused
	declaration.
	(__formatter_chrono::_M_format_to_ostream): Add explicit
	handling for specializations of __local_time_fmt, including the
	time zone abbreviation in the output if __is_neg is true.
	(formatter<chrono::tai_time<D>>::format): Add comment.
	(formatter<chrono::gps_time<D>>::format): Likewise.
	(formatter<chrono::__detail::__local_time_fmt::format): Call
	_M_format with true for the __is_neg flag.
	* testsuite/std/time/clock/gps/io.cc: Remove unused variable.
	* testsuite/std/time/clock/local/io.cc: Fix test error that
	checked tai_time instead of local_time. Add tests for
	local-time-format-t formatting.
	* testsuite/std/time/clock/system/io.cc: Check empty
	chrono-specs.
	* testsuite/std/time/clock/tai/io.cc: Likewise.
	* testsuite/std/time/zoned_time/io.cc: Likewise.

This uses remove_cv_t<T> for the default template argument used for
deducing a type for a braced-init-list used with std::optional and
std::expected.

libstdc++-v3/ChangeLog:

	* include/std/expected (expected(U&&), operator=(U&&))
	(value_or): Use remove_cv_t on default template argument, as per
	LWG 3886.
	* include/std/optional (optional(U&&), operator=(U&&))
	(value_or): Likewise.
	* testsuite/20_util/expected/lwg3886.cc: New test.
	* testsuite/20_util/optional/cons/lwg3886.cc: New test.

'dg-compile' is not a thing, replace it with 'dg-do compile'.

	PR target/68015
	PR c++/83979
	* c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo.
	* g++.dg/pr83979.C: Likewise.
	* g++.target/aarch64/sve/acle/general-c++/attributes_2.C: Likewise.
	* gcc.dg/tree-ssa/builtin-sprintf-7.c: Likewise.
	* gcc.dg/tree-ssa/builtin-sprintf-8.c: Likewise.
	* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Likewise.
	* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: Likewise.
	* gcc.target/s390/20181024-1.c: Likewise.
	* gcc.target/s390/addr-constraints-1.c: Likewise.
	* gcc.target/s390/arch12/aghsghmgh-1.c: Likewise.
	* gcc.target/s390/arch12/mul-1.c: Likewise.
	* gcc.target/s390/arch13/bitops-1.c: Likewise.
	* gcc.target/s390/arch13/bitops-2.c: Likewise.
	* gcc.target/s390/arch13/fp-signedint-convert-1.c: Likewise.
	* gcc.target/s390/arch13/fp-unsignedint-convert-1.c: Likewise.
	* gcc.target/s390/arch13/popcount-1.c: Likewise.
	* gcc.target/s390/pr68015.c: Likewise.
	* gcc.target/s390/vector/fp-signedint-convert-1.c: Likewise.
	* gcc.target/s390/vector/fp-unsignedint-convert-1.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-1.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-2.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-3.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-4.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-5.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-6.c: Likewise.
	* gcc.target/s390/vector/reverse-elements-7.c: Likewise.
	* gnat.dg/alignment15.adb: Likewise.
	* gnat.dg/debug4.adb: Likewise.
	* gnat.dg/inline21.adb: Likewise.
	* gnat.dg/inline22.adb: Likewise.
	* gnat.dg/opt37.adb: Likewise.
	* gnat.dg/warn13.adb: Likewise.

libstdc++-v3/ChangeLog:

	* src/c++17/fs_ops.cc: Fix file name in comment.

	PR target/51492

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr51492.c: New test.

Binutils 2.42 and before don't recognize the b extension in the march
strings even though it supports zba_zbb_zbs. Add a configure check to
ignore the b in the march string if found.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_subset_list::to_string):
	Skip b in march string
	* config.in: Regenerate.
	* configure: Regenerate.
	* configure.ac: Add B assembler check

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>