[PATCH] riscv: add mising masking in lrsc expander (PR118137)

gcc:
	PR target/118137
	* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
	to shifted value.

gcc/testsuite:
	PR target/118137
	* gcc.dg/atomic/pr118137.c: New.

gcc/config/riscv/sync.md

@@ -467,6 +467,7 @@
 
   rtx shifted_value = gen_reg_rtx (SImode);
   riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
+  emit_move_insn (shifted_value, gen_rtx_AND (SImode, shifted_value, mask));
 
   emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem,
 						 shifted_value, model,

gcc/testsuite/gcc.dg/atomic/pr118137.c

+/* Test that subword atomic operations only affect the subword.  */
+/* { dg-do run } */
+/* { dg-require-effective-target sync_char_short } */
+
+void
+foo (char *x)
+{
+  __sync_fetch_and_or (x, 0xff);
+}
+
+void
+bar (short *y)
+{
+  __atomic_fetch_or (y, 0xffff, 0);
+}
+
+
+int
+main ()
+{
+  char b[4] = {};
+  foo(b);
+
+  short h[2] = {};
+  bar(h);
+
+  if (b[1] || b[2] || b[3] || h[1])
+    __builtin_abort();
+}