RISC-V: Limit regs use for z*inx extension.

Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.

Co-Authored-By: Sinan Lin <sinan@isrc.iscas.ac.cn>

gcc/ChangeLog:

	* config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
	use while Zfinx is enable.
	* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
	registers use when Zdinx enable in RV32 cases.
	(riscv_option_override): New target enable MASK_FDIV.
	(riscv_libgcc_floating_mode_supported_p): New error info when
	use incompatible arch&abi.
	(riscv_excess_precision): New target enable FLOAT16.