RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 3.  Aka:

Form 3:
  #define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)                             \
  void __attribute__((noinline))                                        \
  vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
  {                                                                     \
    unsigned i;                                                         \
    for (i = 0; i < limit; i++)                                         \
      {                                                                 \
        WT max = (WT)(NT)-1;                                            \
        out[i] = in[i] <= max ? (NT)in[i] : (NT)max;                    \
      }                                                                 \
  }

DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-13.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-14.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-15.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-16.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-17.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-18.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>