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RISC-V: Add testcases for form 2 of signed vector SAT_ADD
Form 2:
#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T sum = (UT)x + (UT)y; \
if ((x ^ y) < 0 || (sum ^ x) >= 0) \
out[i] = sum; \
else \
out[i] = x < 0 ? MIN : MAX; \
} \
}
DEF_VEC_SAT_S_ADD_FMT_2 (int8_t, uint8_t, INT8_MIN, INT8_MAX)
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c: New test.
Signed-off-by:
Pan Li <pan2.li@intel.com>
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- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c 9 additions, 0 deletions...uite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c 9 additions, 0 deletions...uite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c 9 additions, 0 deletions...uite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c 9 additions, 0 deletions...uite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c 17 additions, 0 deletions.../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c 17 additions, 0 deletions.../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c 17 additions, 0 deletions.../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c 17 additions, 0 deletions.../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c
- gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h 24 additions, 0 deletionsgcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
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